ADC Overflow Handling With Bit-Sum Output for Fast Accuracy

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Solution Overview

Problem

Analog-to-digital converter circuits face accuracy issues due to overflow conditions in pulse delay circuits, leading to anomalous data values and limited resolution and speed.

Innovation Solution

The proposed analog-to-digital converter circuit incorporates a sum output unit that calculates the sum of n-bit and (n+1)-bit data values from first and second output units, respectively, and uses encoders and calculators to manage sign bits and significant bits, preventing anomalous calculations by combining selected bits to generate accurate digital data values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If pulse delay circuits are used for analog-to-digital conversion, then digitizing speed is improved, but accuracy deteriorates due to overflow conditions causing anomalous data values

Engineering Contradiction:
Improvedigitizing speedVSAvoidconversion accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

A sum output unit is introduced as an intermediary component between the first and second output units. This sum output unit calculates the sum of the n-bit data value from the first output unit and the (n+1)-bit data value from the second output unit, thereby mediating the combination of their results to produce accurate digital data values while maintaining high digitizing speed

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sign bit is extracted and separately processed from the (n+1)-bit data value. The second calculator of the second output unit calculates the sum of the sign bit and the second significant bit, and this extracted sign bit information is then combined with the data from the first output unit to generate the final accurate digital output

Inventive Principle:
Principle #2Taking out (Extraction)

2Measurement precision

If higher resolution is achieved through increased data bits, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
ImproveresolutionVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The output data is segmented into different bit components: the first output unit provides an n-bit data value while the second output unit provides an (n+1)-bit data value. This segmentation allows the system to achieve higher resolution by combining these segmented outputs through the sum output unit, rather than requiring a single complex high-resolution output path

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The sum output unit merges the n-bit data value from the first output unit with the (n+1)-bit data value from the second output unit by calculating their sum. This merging operation achieves higher effective resolution by combining the information from both output units without requiring either unit to independently provide the full high resolution

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If overflow conditions are prevented through additional calculation steps, then accuracy is improved, but processing time increases

Engineering Contradiction:
Improvedata accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The sum output unit performs preliminary addition of the data values from the first and second output units. The second calculator also preliminarily calculates the sum of the sign bit and second significant bit. These preliminary calculations are performed in parallel with the main conversion process, preventing overflow conditions without adding sequential processing steps that would increase overall processing time

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12143119B2Analog-to-digital converter circuit
Publication Date: 2024.11.12 DENSO CORP
  • US12143119B2 patent drawing
  • US12143119B2 patent drawing
  • US12143119B2 patent drawing

AI summary

In an analog-to-digital converter circuit, a sum output unit calculates the sum of an n-bit data value outputted from a first output unit and an (n+1)-bit data value outputted from a second output unit to accordingly obtain the calculated sum as a digital data value. A second calculator of the second output unit calculates the sum of a sign bit of a third digital data value as a most significant bit thereof and a second significant bit of the third digital data value. The combines a bit selected from the calculated sum with the third digital data value from which the sign bit has been eliminated to accordingly generate, as the (n+1)-bit data value, a new digital data value whose most significant bit is the bit selected from the calculated sum.