Continuous-Time Pipeline ADC Delay Matching Without Analog Switches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In continuous-time pipeline ADCs (CTP ADCs), achieving precise delay matching between the analog delay element and the ADC-DAC path is challenging, leading to inefficiencies and limitations in analog filter gain and resolution.
Innovation Solution
The proposed solution involves a continuous-time analog-to-digital converter circuit with an analog delay element and an ADC-DAC path, where the delay of the ADC-DAC path is matched to the analog delay element using a delay control device, eliminating the need for switches in the analog path and allowing for increased filter gain and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay matching is performed using conventional methods with switches in the analog path, then delay alignment can be achieved, but the analog filter gain is limited and resolution is reduced
Solution Approach 1:
The patent replaces mechanical switches in the analog path with a digital delay control mechanism. The delay matching is achieved by digitally adjusting the delay of the ADC-DAC path to match the analog delay element, eliminating the need for analog switches. This substitution of mechanical/analog components with digital control enables precise delay matching without limiting the analog filter gain or resolution.
2Reliability
If the delay of ADC-DAC path is made greater than 0.5Ts (for zero order hold DAC), then the basic timing requirement is met, but the delay matching range is limited
Solution Approach 1:
The patent implements a dynamic delay control mechanism that can adjust the delay of the ADC-DAC path. The delay control device enables continuous or discrete adjustment of the delay parameter, allowing the system to adapt to different timing requirements and PVT conditions. This dynamic adjustment capability expands the delay tuning range beyond fixed delay configurations while maintaining reliable timing operation.
Solution Approach 2:
The patent changes the delay parameter of the ADC-DAC path to achieve matching with the analog delay element. By controlling the delay parameter through a delay control device, the system can optimize performance under varying conditions. This parameter adjustment approach enables wider tuning of delay mismatch to account for variations in analog signal delay path due to PVT conditions.
3Device complexity
If analog delay element is used without delay control, then the circuit structure is simple, but delay mismatch variations occur under PVT conditions
Solution Approach 1:
The patent implements a feedback mechanism through a delay control device that monitors and adjusts the delay of the ADC-DAC path. The control device receives information about the delay mismatch and adjusts the delay parameter accordingly to maintain matching under varying PVT conditions. This feedback control ensures reliable delay matching stability while managing the added circuit complexity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A continuous-time analog-to-digital converter circuit (100), comprising: - an input (1) to which an analog input signal (vin) can be applied; - an analog delay element (10a... 10n) being interconnected between the input (1) and a first summation node (20); - an ADC-DAC path interconnected between the input (1) and the first summation node (20), the ADC-DAC path being operative to digitize the analog input signal (vin) and to reconvert the digitized analog input signal back to analog and to subtract the reconverted signal at the first summation node (20), the ADC-DAC path comprising: - a switch (S1) interconnected between the input (1) and a sub ADC (11), the switch being operative to sample the analog input (vin) with a specified sampling rate (fs); - a sub DAC (12a... 12n) interconnected between the sub ADC (11) and the first summation node (20), wherein delays of the analog delay element (10a... 10n) and the ADC-DAC path are matched by means of a delay control element (50), wherein an output (r) at the first summation node (20) is filtered by a filter element (30), wherein an output of the filter element (30) is sampled by the specified sampling rate (fs); and - a backend ADC (41) connected to a second summation node (43) and being operative to digitize the sampled output of the filter element (30); wherein the ADC-DAC path is operative to match its delay to the delay (td) of the analog delay element (10a... 10n).