Time-Interleaved ADC Timing Calibration Using Bit-Scaled Correlation

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Solution Overview

Problem

High-speed analog-to-digital conversion using multiple ADCs in a time-interleaving manner leads to data distortion due to time skew errors, degrading the performance of ADC circuits.

Innovation Solution

An ADC circuit with a control logic circuit that calculates correlation values between data output from multiple ADCs using different numbers of bits and times, allowing for efficient calibration of sampling timing to minimize power consumption and time required for correlation calculations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple ADCs are used in a time-interleaving manner to enhance conversion speed, then the conversion speed is improved, but time skew errors occur between multiple ADCs leading to data distortion

Engineering Contradiction:
Improveconversion speedVSAvoiddata accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent changes the parameter of correlation calculation by using different numbers of bits (first number of bits vs. second number of bits) and different numbers of times (first number of times vs. second number of times) to calculate correlation values at different calibration stages. This parameter variation enables efficient calibration that achieves accurate time skew compensation without excessive computational overhead, thus maintaining data accuracy while supporting high-speed time-interleaved operation.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If calibration methods are used to correct time skew errors, then data accuracy is improved, but power consumption and calculation time increase

Engineering Contradiction:
Improvedata accuracyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by using a first number of bits (less than the full resolution) for initial correlation calculations, and only using the full second number of bits for final calibration. This partial use of computational resources reduces power consumption and calculation time while still achieving sufficient calibration accuracy, avoiding the need to always use full-precision calculations.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements periodic calibration by calculating correlation values a first number of times during calibration phases, then using these accumulated correlation values to adjust sampling timing. This periodic approach concentrates computational effort during calibration intervals rather than continuously, reducing overall power consumption while maintaining accurate time skew compensation during normal operation.

Inventive Principle:
Principle #19Periodic action

3Reliability

If calibration methods are used to correct time skew errors, then data accuracy is improved, but the time required for calibration increases

Engineering Contradiction:
Improvedata accuracyVSAvoidcalibration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent uses a first number of bits (partial precision) for initial correlation calculations during calibration, requiring fewer computational operations than full-precision calculations. This partial action approach reduces the time required for calibration while still achieving sufficient correlation values to perform effective time skew compensation, thereby reducing calibration time without sacrificing essential accuracy.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent performs preliminary correlation calculations using a first number of bits to obtain initial correlation values before performing final calibration with the full second number of bits. This preliminary action provides a head start in the calibration process, reducing the overall calibration time by having preliminary correlation data ready before the final high-precision calibration step.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4572149A1Analog-to-digital converter circuit, an electronic device including the same and a method for controlling the same
Publication Date: 2025.06.18 SAMSUNG ELECTRONICS CO LTD
  • EP4572149A1 patent drawingFigure 1
  • EP4572149A1 patent drawingFigure 2A~2B
  • EP4572149A1 patent drawingFigure 3

AI summary

An ADC circuit including: ADCs to perform conversion operations in a time-interleaving manner; and a control logic circuit connected to the ADCs, wherein the control logic circuit is configured to: calculate a correlation value between data output from the ADCs a first number of times using a first number of bits among each bit of the data; calibrate a sampling timing of at least some of the ADCs, based on a first cumulative correlation value, which is obtained by accumulating correlation values calculated the first number of times; calculate the correlation value between the data a second number of times by using a second number of bits in each of the data; and calibrate the sampling timing of the at least some of the ADCs, based on a second cumulative correlation value, which is obtained by accumulating correlation values calculated the second number of times.