Pipeline ADC Reference Circuit for Inter-Stage Gain Error Reduction

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Solution Overview

Problem

Pipeline analog-to-digital converters (ADCs) face inter-stage gain errors due to mismatches in reference voltages between stages, leading to inaccurate digital outputs, decreased signal-to-noise ratio, and increased harmonic distortion.

Innovation Solution

The implementation of a pipeline ADC with reference generation circuitry that generates a low voltage reference proportional to a high voltage reference, reducing inter-stage gain errors by ensuring the low voltage reference is proportional to the high voltage reference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a pipeline ADC uses multiple stages with different reference voltages to achieve high-speed conversion, then conversion speed is improved, but inter-stage gain errors increase due to reference voltage mismatches

Engineering Contradiction:
Improveconversion speedVSAvoiddigital output accuracy
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent changes the reference voltage parameter by generating a low voltage reference that is precisely proportional to the high voltage reference through a voltage divider network. This ensures that the reference voltage relationship between stages is maintained accurately, eliminating inter-stage gain errors while preserving high-speed conversion capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces an intermediary voltage divider network consisting of resistors and capacitors that mediates between the high voltage reference and the low voltage reference. This intermediary circuit ensures precise proportional relationship and eliminates direct mismatches between reference voltages of different stages

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If reference voltage mismatches occur between stages, then device complexity is reduced, but signal-to-noise ratio decreases and harmonic distortion increases

Engineering Contradiction:
Improvereference generation structureVSAvoidsignal-to-noise ratio and harmonic distortion
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent precisely controls the reference voltage parameter through a voltage divider network with carefully selected resistor and capacitor values. This ensures the low voltage reference is exactly proportional to the high voltage reference, eliminating the harmful effects of reference mismatches on signal quality

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The voltage divider network acts as an intermediary that precisely establishes the proportional relationship between reference voltages. By using matched resistors and capacitors, the network ensures accurate voltage division without introducing additional noise or distortion

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces inter-stage gain errors, leading to more accurate digital outputs, improved signal-to-noise ratio, and reduced harmonic distortion in pipeline ADCs.

Implementation Method 1

a capacitor coupled in parallel to the second resistor by a switch

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a first resistor coupled to the reference voltage; a second resistor coupled to the first resistor

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS12206424B2Methods and apparatus to reduce inter-stage gain errors in analog-to-digital converters
Publication Date: 2025.01.21 TEXAS INSTRUMENTS INC
  • US12206424B2 patent drawing
  • US12206424B2 patent drawing
  • US12206424B2 patent drawing

AI summary

An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.