Range Profile Digitization Circuit for Fast Low-Noise Radar Sampling
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Solution Overview
Problem
Existing impulse radar systems face limitations in high-speed range profile digitization due to slow rise and fall times of quantized signals, leading to missed counts and erroneous signal digitization, and high switching noise at high frequencies, which affects the accuracy and reliability of signal sampling.
Innovation Solution
A range profile digitization circuit that re-uses samplers with multiple decoders and a demultiplexer, reducing capacitive load and enabling faster signal capture, along with a controller generating regular trigger signals using a multiphase frequency generator to ensure continuous and reliable sampling, and employing a differencer to delay quantization until after sampling, reducing switching noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional ADCs are used for signal digitization, then amplitude resolution can be achieved, but sampling speed is limited and cannot keep up with high PRF signals
Solution Approach 1:
The signal digitization process is segmented into two distinct stages: first, a 1-bit comparator performs ultra-fast sampling at PRF rates to capture time resolution, producing a thermometer-coded output; second, a counter accumulates these binary samples over multiple pulses to build up amplitude resolution. This segmentation allows each stage to optimize for its specific function without compromising the other.
Solution Approach 2:
The system uses periodic repetition of the transmitted pulse and corresponding reception windows to accumulate multiple 1-bit samples for each range bin. By sweeping the threshold voltage across multiple periodic cycles and counting the high-state occurrences, the system converts temporal periodicity into amplitude resolution, achieving high precision through time-averaging rather than instantaneous high-resolution measurement.
2Measurement precision
If swept-threshold digitization is used to achieve high resolution in both time and amplitude, then measurement precision improves, but device complexity increases due to multiple parallel counters and delay lines
Solution Approach 1:
The 1-bit comparator serves multiple functions simultaneously: it acts as an ultra-fast ADC for time resolution, a threshold detector for amplitude encoding, and a trigger for the counting process. The single comparator output drives multiple range bins through the delay line, making one component serve the entire digitization function rather than requiring separate ADCs for each range bin.
Solution Approach 2:
The system merges the functions of multiple high-resolution ADCs into a single 1-bit comparator combined with a counting mechanism. Instead of parallelizing multiple complex ADC circuits, the invention parallelizes simple binary counters and combines their inputs through a single comparator, reducing overall circuit complexity while maintaining or improving measurement precision.
3Productivity
If multiple parallel counters are used to sample multiple range points simultaneously, then productivity increases, but capacitive load increases causing slower rise and fall times and missed counts
Solution Approach 1:
The 1-bit comparator output serves as an intermediary signal that mediates between the analog input signal and the multiple digital counters. The comparator converts the analog signal into a clean binary waveform that can reliably drive multiple counter inputs without the capacitive loading issues of direct analog-to-multiple-digital connections. This intermediary binary stage isolates the counters from each other's capacitive effects.
4Device complexity
If early quantization is performed before sampling, then signal processing is simplified, but switching noise increases affecting sampling accuracy
Solution Approach 1:
The system performs preliminary sampling of the analog signal at ultra-fast rates using the 1-bit comparator before any quantization or digital processing occurs. This preliminary action captures the signal's temporal characteristics in the analog domain, and only after sampling is complete does the system quantize the accumulated counts into digital amplitude values. This sequencing eliminates switching noise during the critical sampling phase.
Data Source
AI summary
A range profile digitization circuit for converting a repeating analog input signal into a time series of digital amplitude values, the converter comprising: a signal quantizer arranged to receive the analog input signal and a threshold input and arranged to output a binary value quantized output signal based on a comparison of the input signal with the threshold signal; a plurality of samplers each arranged to sample and hold its input signal upon receipt of a trigger signal; and for each sampler: a plurality of decoders and a demultiplexer arranged to receive an output from the sampler and pass it to a selected one of said decoders based on a selector input. With a plurality of decoders associated with each of the samplers, each sampler can be re-used during the building up of the range profile.