Delay-Based ADC Comparator With Voltage-to-Time Conversion
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Solution Overview
Problem
Conventional comparators in high-speed ADCs require input signals to be held for a relatively long period, leading to slowed operation and increased timing complexities due to their slow decision-making time, typically greater than 100 ps in 65 nm technology.
Innovation Solution
A high-speed latch comparator is developed, incorporating a voltage-controlled delay circuit that converts input voltage information into time information, allowing the input clock to be delayed proportionally to the input voltage, thereby reducing decision time to approximately 25 ps and eliminating the need for holding input information during the decision-making process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional comparators are used in high-speed ADCs, then the comparator can perform basic comparison function, but the decision-making time is slow (greater than 100 ps) requiring input signals to be held for a long period
Solution Approach 1:
The patent applies dynamics by making the delay time variable rather than fixed. The delay circuit adjusts the delay time of the clock signal dynamically based on the input signal characteristics, allowing the comparator to optimize its decision-making time for each specific input condition. This dynamic adjustment enables faster decision-making (reducing to approximately 25 ps) without requiring long-term holding of input signals.
Solution Approach 2:
The patent changes the time delay parameter of the clock signal to optimize comparator performance. By varying the delay time parameter based on input voltage levels, the comparator can adapt its decision-making speed to match the specific requirements of different input signals, thereby achieving high-speed operation without prolonged signal holding.
2Device complexity
If conventional comparators with long decision-making time are used, then the circuit operation is simplified, but timing complexities increase and input information may be corrupted
Solution Approach 1:
The dynamic delay adjustment mechanism allows the comparator to automatically adapt to different timing requirements without requiring complex external timing control circuits. The delay circuit responds dynamically to input signal characteristics, simplifying the overall system timing management while reducing timing complexities.
Solution Approach 2:
The comparator performs self-adjustment of its timing parameters through the delay circuit that automatically responds to input signal conditions. This self-service capability eliminates the need for complex external timing control and reduces timing complexities in the overall system.
3Productivity
If the decision-making time is reduced to approximately 25 ps, then the comparator speed increases, but the circuit requires more complex delay control mechanisms
Solution Approach 1:
The delay control mechanism operates autonomously by responding directly to input signal characteristics. The circuit self-adjusts the delay time without requiring complex external control logic, thereby achieving high processing speed (approximately 25 ps decision time) while keeping the control mechanism relatively simple.
Solution Approach 2:
The delay circuit acts as an intermediary between the clock signal and the comparison operation. It mediates the timing relationship by introducing a variable delay that is automatically adjusted based on input conditions, enabling high-speed operation without requiring complex direct control of the comparison process.
Data Source
AI summary
An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.