Analogue/Digital Conversion TRIZ Cases

Digital photon discrimination and timing replace analog circuitry to avoid signal distortion and improve fast, reliable single-photon counting.

A current-mode time-interleaved charge sampler replaces voltage buffers and high-order filters to cut 5G receiver power and area.

A precharged bootstrap capacitor keeps gate-source voltage stable, cutting input loading and harmonic distortion in high-speed RF sampling.

Combining TDC phase samples with cycle counting improves frequency resolution and speed while reducing drift from long measurement windows.

A correction term derived from analog matrix-vector results decouples and rectifies crossbar nonlinearity without sacrificing compute speed.

Using the transistor bulk terminal as a DAC cuts area, power, and noise in biopotential input circuits while preserving low-frequency signals.

Parallel charge aggregation replaces register-based intermediate storage, speeding multiply-accumulate operations and simplifying logic for AI workloads.

Half-cycle signal comparison detects short-tooth markers on high-speed rotating shafts while limiting phase delay, noise, and processing load.

A buffered floating-ground and balanced output circuit suppresses ground-loop noise in single-ended analog audio reception.

Dynamic chop clock control shifts or disables chopping to suppress intermodulation spurs and improve current and voltage sensing accuracy.

A gated ring oscillator replaces DLL-based analog clock generation, enabling calibrated edge clocks with programmable phase and duty cycle at smaller nodes.

A pipelined multi-level receiver selects reference voltages from an initial bit to cut sense amplifiers, power use, and circuit size.

Correlated triple sampling compensates TFT variation and background noise in X-ray sensor readout, improving ADC range and signal resolution.

By slicing analog input signals into analog and digital paths, this case improves RF front-end dynamic range and linearity without excessive ADC power.

A static analog calibration circuit tunes sampler current against PVT variation, keeping high-speed data detection accurate across dies and conditions.

Asynchronous pattern-verified sampling guides CTLE bandwidth tuning to counter attenuation and inter-symbol interference in high-speed links.

Coarse and fine gain control in an analog front end limits transient SNR shifts, clipping, and packet loss under temperature drift.

A shared catheter electrode is used to estimate ground and timing offsets, enabling accurate synchronized unipolar ECG acquisition.

Series-connected differential channels split large input voltages and combine outputs to improve ADC accuracy without precise component matching.

Reference delay matching detects and corrects phase interpolator INL across PVT and signal variations, reducing jitter and power use.

Fly-back current sensing replaces tolerance-sensitive bridge and oscillator circuits to deliver higher-resolution inductance measurement with fewer components.

Adaptive reference voltage feedback across time-interleaved ADCs improves PAM-n bit detection under attenuation and distortion.

A master radar chip aligns ADC clocks and ramp timing across slave chips to reduce phase errors and preserve coherent multi-channel sampling.

A serial Bluetooth protocol switch transfers call history and phone book data first, then enables stable in-vehicle handsfree calling.

Edge combining with a DTC and delta-sigma modulation cuts fractional divider jitter while improving frequency accuracy for crystal replacement.

Negative phase stepping and layered retiming synchronize interleaved clock signals with better timing margin, throughput, and power efficiency.

Binary-search calibration tunes ADC reference voltage and divider resistance to match each pressure sensor and reduce quantization noise.

Integrated photocurrent during brief LED emission enables accurate pulse wave sensing with lower LED and amplifier power in wearables.

Periodic current-driven weight voltage and capacitor charge summation cut power use while sustaining multi-bit neural MAC throughput.

High-voltage sensing with low-voltage readout lets MEMS seismic acquisition improve accuracy and range while cutting power and heat.

Cross-coupled OCMFB capacitors reuse feedback current to boost gain, cutting load-driven power loss and settling time in dynamic residue amplifiers.

Analog sensor signals are converted into asynchronous duty-cycle streams to cut power and clock overhead while preserving precise on-device processing.

Dynamic AAF reconfiguration and nested chopping reduce ADC offset, improve settling symmetry, and mask unsettled conversion data.

A single sensor interface outputs results, digitized signals, and characterization data so external processing can verify reliability without redundant sensors.

Periodic bias application and latch-based offset correction cut memristor neural circuit power and scale without losing calculation accuracy.

Separate low- and high-temperature compensation currents correct analog offset drift smoothly across temperature ranges without signal discontinuities.

Synchronized ADC sampling across multiple magnetic sensors cuts timing mismatch errors and improves angle detection accuracy.

A controller widens or narrows sensor filter passband by signal change, cutting noise without adding delay during rapid feedback.

Cross-correlation with a higher-rate return template improves laser scanner distance resolution without costly high-speed sampling hardware.

Clamping high-speed DAC-to-ADC signals to fractional supply rails cuts pattern-dependent ISI, improves signal integrity, and lowers bit errors.

A reconfigurable sum-difference modulator lets one Class-D amplifier support dual single-ended and differential outputs with common-mode control.

Digitized noise amplitude and phase recovery enables analog cancellation of 50/60 Hz narrowband interference in very low-amplitude signals.

A CMOS grounded capacitance multiplier uses digital current gain control to create large equivalent capacitance without large on-chip capacitors.

Bleed air pressure trends let an APU diagnose power compressor deterioration without extra sensors, improving targeted maintenance and reliability.

A voltage-controlled delay circuit converts input voltage into timing, cutting ADC comparator decision time and easing input-hold constraints.

Pattern-verified asynchronous samples estimate frequency-specific voltages, letting CTLE settings compensate attenuation and inter-symbol interference.

Adjustable PWM quantizer gain compensates driver voltage swing changes to keep Class-D speaker output gain stable across modes.

FFT-based segmentation of ADC-captured wideband signals enables continuous spectral monitoring with adjustable resolution and lower equipment burden.

By analyzing only peak- or trough-based signal snapshots, this circuit evaluates generator non-linearity with lower processing overhead and better correction.

Adaptive noise mixing uses temperature and interference analysis to suppress sensor artifacts and improve signal-to-noise ratio.