Digital Clock Phase Generation Without DLL Using a Gated Ring Oscillator
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Solution Overview
Problem
Existing clock generation circuits for SAR ADCs rely on complex analog circuits, such as DLLs, which do not scale well with reduced process nodes, limiting their performance and scalability.
Innovation Solution
A digitally calibrated generating circuit using a gated ring oscillator that provides a reference clock with a higher fundamental frequency than the input clock, allowing for programmable adjustment of clock edges and duty cycles without a DLL, enabling scalable and rapid edge clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a DLL is used to generate multiple clock edges in a period of the input clock, then the clock phase generation capability is improved, but the device complexity and scalability worsen
Solution Approach 1:
The patent replaces the analog delay-locked loop (DLL) mechanism with a digital clock generation approach using a ring oscillator and counter system. The ring oscillator generates a high-frequency reference clock that is divided down to the input clock frequency, and digital counters generate the required clock edges. This substitution of analog with digital circuitry eliminates the scalability issues of analog DLLs while maintaining the ability to generate multiple clock phases.
Solution Approach 2:
The patent changes the fundamental frequency parameter of the clock generation system by using a ring oscillator that operates at a frequency higher than the input clock. By programmatically adjusting the oscillator frequency and counter values, the system can generate multiple clock edges within a single input clock period without requiring complex analog delay elements.
2Manufacturing precision
If process nodes are reduced to smaller critical dimensions, then the manufacturing precision is improved, but the reliability of analog circuits in DLL worsens
Solution Approach 1:
The patent substitutes analog circuit elements with digital logic components. The ring oscillator uses digital logic gates instead of analog delay elements, and the clock edge generation uses digital counters and latches. This digital implementation is inherently more robust to process variations and scaling effects, maintaining reliability as process nodes are reduced.
Solution Approach 2:
The system includes calibration circuitry that automatically adjusts the ring oscillator frequency and counter values to compensate for process variations. The calibration process measures the actual clock periods and programmatically corrects any deviations, making the system self-adjusting and reliable across different process nodes without requiring manual tuning or complex analog compensation circuits.
3Productivity
If a gated ring oscillator is used to generate a reference clock with higher fundamental frequency, then the productivity of clock edge generation is improved, but the device complexity increases
Solution Approach 1:
The patent segments the clock generation function into distinct digital components: a ring oscillator for frequency generation, counters for frequency division and phase generation, and control logic for coordination. This segmentation allows each component to be optimized independently and implemented using standard digital logic cells, making the overall system more manageable and potentially more efficient than a monolithic analog approach.
Data Source
AI summary
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.