Pipeline Multi-Level Receiver Using Adaptive Reference Selection
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently processing multi-level signals with reduced power consumption and circuit size while maintaining performance, particularly in receivers with pipeline structures for volatile and nonvolatile memory applications.
Innovation Solution
A receiver configuration that includes a sample and hold circuit, a first analog-to-digital converting circuit, a digital-to-analog converting circuit, and a second analog-to-digital converting circuit, which generates multi-bit data by sampling and holding multi-level signals, selecting reference voltages based on output data bits, and generating additional bits using these circuits in a pipeline scheme to reduce the number of sense amplifiers and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional receiver structure with multiple sense amplifiers is used to process multi-level signals, then measurement precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The receiver is divided into multiple pipeline stages, with each stage containing a sense amplifier and reference voltage generator. Each stage processes a portion of the multi-level signal by comparing against specific reference voltages, breaking down the complex multi-level detection into simpler binary decisions that can be made sequentially through the pipeline stages.
Solution Approach 2:
Reference voltages are pre-generated and stored in reference voltage generators before the signal processing begins. The pipeline structure pre-positions multiple sense amplifiers with their respective reference voltages, allowing rapid sequential comparison without requiring dynamic voltage adjustment during the detection process.
2Productivity
If multiple sense amplifiers are used to handle multi-level signals, then productivity is improved, but use of energy increases
Solution Approach 1:
The high-speed data processing task is segmented across multiple pipeline stages, where each sense amplifier processes a specific comparison operation. This allows parallel processing capability while maintaining lower power consumption per stage, as each amplifier operates independently on a simplified binary decision rather than handling the full multi-level complexity.
Solution Approach 2:
The pipeline structure enables periodic processing of signal levels through sequential stages. Each stage processes its specific reference voltage comparison in a rhythmic fashion, allowing the system to maintain high throughput by continuously cycling through the pipeline stages with regular clocking, while individual sense amplifiers can be powered down or operated at lower power when not actively processing.
3Device complexity
If a simplified receiver structure with fewer sense amplifiers is used, then device complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The receiver transitions from attempting to detect all multi-level signals simultaneously in a single stage to processing them sequentially through multiple time-dimensional stages. Each sense amplifier operates in its own time slot within the pipeline, comparing the signal against its specific reference voltage, thereby achieving accurate multi-level detection through temporal dimensionality rather than spatial parallelism.
4Measurement precision
If multiple reference voltages are simultaneously compared, then measurement precision is improved, but loss of time increases
Solution Approach 1:
Multiple reference voltages are pre-generated and held ready in dedicated reference voltage generators before the comparison process begins. This eliminates the time required to generate or switch reference voltages during processing, as each pipeline stage has its reference voltage already prepared and stable, ready for immediate comparison with the input signal.
Solution Approach 2:
The comparison process proceeds periodically through the pipeline stages in a sequential manner. Each stage performs its voltage comparison at a regular interval determined by the clock signal, creating a rhythmic processing flow that efficiently utilizes the available time while maintaining accurate multi-level detection through the systematic progression through all reference voltage comparisons.
Data Source
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Figure 2A~2B
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AI summary
A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.