Parallel Charge-Aggregating MAC Circuit Without Register Delays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multiply-accumulate circuits in digital signal processors perform multiplication and addition operations serially, leading to performance bottlenecks and delays, especially in modern real-time artificial intelligence applications where the number of product pairs increases.
Innovation Solution
A multiply-accumulate circuit that includes a memory for storing operands, computation circuits for generating charges from product pairs, and an aggregator circuit to aggregate these charges, allowing for parallel processing and reducing the need for intermediate storage and computational logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple MACs are employed to perform digital multiplications in parallel, then the performance is improved, but it introduces delays in storing and reading intermediate results and adds complications to control logic
Solution Approach 1:
The patent extracts the intermediate result storage function from traditional digital registers and relocates it to an analog memory array. This eliminates the need for digital read/write operations during the computation process, thereby removing the delays associated with storing and reading intermediate results while maintaining parallel computation capabilities
Solution Approach 2:
The patent replaces the digital mechanical system of storing intermediate results in registers with an analog system where intermediate results are directly maintained as voltage signals in the memory array. This substitution eliminates the discrete read/write cycles required in digital systems, thereby eliminating the associated time delays
2Device complexity
If conventional digital MAC operations are performed serially, then the logic complexity is reduced, but the system performance is significantly reduced
Solution Approach 1:
The patent replaces the digital sequential processing system with an analog parallel processing system. In the analog domain, multiple multiply-accumulate operations can be performed simultaneously across the memory array without requiring complex digital control logic, thereby achieving both high performance and simplified logic
Solution Approach 2:
The patent creates a universal analog computation platform where the same memory array structure can perform multiple multiply-accumulate operations in parallel. This multi-functional approach allows the system to handle various computational tasks simultaneously, achieving high productivity without increasing logic complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves the speed and efficiency of multiply-accumulate operations by enabling parallel processing of product pairs and reducing computational and storage overhead, enhancing performance in AI applications.
Implementation Method 1
a plurality of computation circuits configured to generate a plurality of charges according to the plurality of product pairs
Data Source
AI summary
A multiply-accumulate circuit and methods for using the same are disclosed. In one embodiment, a multiply-accumulate circuit includes a memory configured to store a first set of operands and a second set of operands, where the first set of operands and the second set of operands are cross-multiplied to form a plurality of product pairs, a plurality of computation circuits configured to generate a plurality of charges according to the plurality of product pairs, and an aggregator circuit configured to aggregate the plurality of charges from the plurality of computation circuits to record variations of charges, where the variation of charges represent an aggregated value of the plurality of product pairs.