Clocked Data Sampler Calibration for PVT-Stable Detection

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Solution Overview

Problem

Clocked dynamic sampler circuits face stability and accuracy issues due to variations in transistor parameters such as gate threshold voltage, gain, and channel resistance across different integrated circuit dies and over temperature and supply voltage changes, leading to inconsistencies in data detection accuracy.

Innovation Solution

A static analog calibration circuit is used as a measurement proxy to generate a process-voltage-temperature (PVT)-dependent reference voltage, which is compared to the output voltage of a static analog calibration circuit to adjust the current through the clocked data sampler, thereby calibrating the sampler and mitigating the effects of these variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If clocked dynamic sampler circuits are used for high-speed data detection, then productivity is improved, but reliability deteriorates due to transistor parameter variations

Engineering Contradiction:
Improvedata detection speedVSAvoiddata detection accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by performing calibration of the clocked dynamic sampler circuits before actual high-speed data detection operations. The calibration process pre-adjusts the sampler parameters to compensate for transistor variations, ensuring accurate detection during subsequent high-speed operations without requiring continuous calibration that would reduce productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the calibration process measures actual sampler performance and uses this information to adjust control signals that optimize sampler operation. This closed-loop approach ensures that despite transistor parameter variations, the sampler maintains high detection accuracy while operating at high speeds.

Inventive Principle:
Principle #23Feedback

2Adaptability or versatility

If transistor parameters are allowed to vary with PVT conditions, then adaptability is improved, but manufacturing precision deteriorates

Engineering Contradiction:
ImprovePVT condition toleranceVSAvoidsampler performance consistency
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by dynamically adjusting sampler operating parameters based on measured PVT conditions. The calibration circuit modifies control signals to compensate for process, voltage, and temperature variations, allowing the sampler to adapt to different operating conditions while maintaining consistent detection accuracy across manufacturing variations.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3954046B1Dynamic integration time adjustment of a clocked data sampler using a static analog calibration circuit
Publication Date: 2023.03.22 KANDOU LABS SA
  • EP3954046B1 patent drawingFigure 1
  • EP3954046B1 patent drawingFigure 2
  • EP3954046B1 patent drawingFigure 3

AI summary

Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.