Fractional Output Divider With DTC Edge Combining for Low Jitter
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Solution Overview
Problem
Current fractional output dividers used in oscillators suffer from high jitter and poor frequency accuracy, limiting their replacement of crystal oscillators due to noise-induced clock signal deviations and limited frequency ranges.
Innovation Solution
The implementation of a bulk acoustic wave (BAW) oscillator system with a digital to time converter (DTC) and delta sigma modulator (DSM) that reduces jitter through edge combining methods, dynamic reset circuits, and custom low dropout regulators, improving frequency accuracy and enabling higher frequency outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional fractional output dividers are used, then device complexity is reduced, but jitter increases and frequency accuracy deteriorates
Solution Approach 1:
The fractional output divider is divided into multiple functional blocks: integer divider, delta-sigma modulator, digital-to-time converter, and edge combining circuit. Each block performs a specific function to progressively improve frequency accuracy while managing complexity through modular design.
Solution Approach 2:
A digital-to-time converter is introduced as an intermediary component between the digital control signal and the clock signal processing. This mediator converts digital codes into precise time delays, enabling accurate frequency synthesis without directly complicating the core divider circuit.
2Reliability
If conventional fractional output dividers are used, then device complexity is reduced, but jitter increases
Solution Approach 1:
Multiple clock edges from different division paths are combined in the edge combining circuit to generate the final output. This merging of multiple signal paths averages out jitter variations and produces a cleaner output signal with reduced jitter, while the modular structure keeps individual circuit blocks relatively simple.
Solution Approach 2:
The delta-sigma modulator employs periodic switching and noise shaping techniques to systematically manage quantization noise and jitter. By using periodic action in the modulation process, the circuit achieves low jitter performance through structured signal processing rather than complex filtering.
3Adaptability or versatility
If crystal oscillators are replaced by fractional output dividers, then adaptability improves, but frequency accuracy deteriorates
Solution Approach 1:
The fractional output divider circuit serves multiple functions: it can generate a wide range of output frequencies through programmable division ratios, while simultaneously maintaining high frequency accuracy through the precision time delay mechanism. This multi-functionality allows replacement of crystal oscillators with improved adaptability without sacrificing accuracy.
Solution Approach 2:
The system achieves different frequency outputs by changing the digital control parameters fed to the delta-sigma modulator and digital-to-time converter. By varying these parameters, the circuit can accurately synthesize any frequency within its range, providing both the adaptability to replace crystal oscillators and the precision needed for accurate frequency generation.
Data Source
AI summary
An example digital to time converter includes: a first switch having a first terminal, a second terminal, and a first control terminal configured to receive a control signal. A second switch having a third terminal coupled to second terminal, a fourth terminal, and a second control terminal configured to receive a divided clock signal. A third switch having a fifth terminal coupled to the second terminal and the third terminal, a sixth terminal, and a third control terminal configured to receive an inverted version of divided clock signal. A fourth switch having a seventh terminal coupled to the second terminal, an eighth terminal, and a fourth control terminal configured to receive an inverted version of control signal. A fifth switch having a ninth terminal coupled to the eighth terminal and a fifth control terminal configured to receive the inverted divided clock signal. A capacitor coupled to the sixth terminal.