Asynchronous Stream Mote for Low-Power Sensor Processing
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Solution Overview
Problem
Conventional stochastic computing methods face limitations in achieving low-power, compact designs due to requirements for long and independent stochastic streams, which are expensive to generate and maintain, and result in significant power overhead and timing constraints, while also requiring expensive random number generators and synchronous stream generation.
Innovation Solution
The implementation of asynchronous stream generators and processors that convert analog signals into asynchronous streams with a duty factor based on signal magnitude, allowing for asynchronous processing and wireless transmission using impulse radio ultra-wide band transmitters, eliminating the need for synchronous clocks and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional stochastic computing uses long and independent stochastic streams to achieve accurate and precise processing, then processing accuracy and precision are improved, but power consumption increases and device complexity increases due to expensive random number generators and synchronous stream generation
Solution Approach 1:
The patent replaces conventional synchronous stochastic computing mechanisms (random number generators, synchronous clocks) with an asynchronous stream processing system. Analog signals are directly converted to asynchronous streams without requiring random number generation or synchronous clock distribution, thereby reducing power consumption while maintaining processing precision through duty-cycle-encoded streams
Solution Approach 2:
The patent changes the fundamental parameter representation from synchronous binary streams to asynchronous duty-cycle-encoded streams. The magnitude of analog signals is represented by the duty factor (ratio of high to total duration) of asynchronous streams, allowing accurate and precise processing without requiring long independent streams or high-frequency clocks
2Reliability
If conventional stochastic computing uses synchronous stream generation with fast clocks to meet timing constraints, then stream synchronization is improved, but power overhead and device complexity increase due to clock distribution requirements
Solution Approach 1:
The patent inverts the conventional approach by eliminating synchronous clock distribution entirely. Instead of using fast synchronous clocks to enforce timing constraints, the system uses asynchronous event-driven processing where streams are processed when events occur, naturally handling synchronization without power-hungry clock networks
Solution Approach 2:
The patent substitutes the mechanical synchronous clock distribution system with an asynchronous event-driven control mechanism. Stream processing is triggered by event occurrences rather than clock edges, eliminating the need for fast clocks and complex timing constraint management while maintaining reliable processing
3Area of stationary object
If conventional stochastic computing uses simple logic gates for serial processing to reduce area and power, then area and power are reduced, but processing speed decreases due to serial operation requirements
Solution Approach 1:
The patent introduces dynamic asynchronous processing where the processing speed adapts to the event rate of the input streams. Simple logic gates operate at the natural event rate rather than a fixed synchronous clock rate, allowing the circuit to process faster when events are frequent while maintaining low area and power consumption through the simplicity of the logic gate implementation
Data Source
AI summary
Asynchronous stream generation and processing techniques are described that support implementation of an asynchronous stream mote in which one or more analog sensor signals are used to generate one or more asynchronous streams. On-device operations processing of the one or more asynchronous streams may be performed before transmission of the result(s) to other system components (e.g., peer motes or higher-level system components).