Time-Interleaved ADC Down-Conversion for Timing Skew Compensation
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face significant performance issues due to timing skew errors, which are challenging to accurately compensate using existing methods, especially in high-performance ADC systems, as traditional approaches either require complex and power-hungry digital implementations or are inadequate for signals with repeated patterns or changing statistics.
Innovation Solution
The integration of a timing skew correction function within the signal down-conversion block using a numerically controlled oscillator (NCO) allows for accurate compensation of timing offsets with minimal power consumption, leveraging existing digital functions in a digital down-converter (DDC) and employing discrete Fourier transform (DFT) for phase error estimation and compensation, thereby reducing hardware overhead and maintaining high accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional digital timing skew correction methods are used, then timing skew compensation accuracy is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent combines the timing skew correction function with the existing digital down-conversion block by integrating a numerically controlled oscillator (NCO). This merging allows the NCO to perform both frequency synthesis and timing skew compensation, eliminating the need for separate correction hardware and reducing overall power consumption while maintaining high accuracy.
Solution Approach 2:
The NCO is designed to serve multiple functions: frequency synthesis for down-conversion and timing skew compensation. By making the NCO universal, the patent avoids adding dedicated correction circuits, thereby reducing device complexity and power consumption while achieving accurate timing skew correction.
2Measurement precision
If additional digital blocks are added for timing skew correction, then timing skew compensation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the timing skew correction functionality into the existing digital down-conversion block by utilizing the NCO. This integration eliminates the need for additional standalone correction circuits, thereby reducing hardware overhead and device complexity while maintaining high compensation accuracy.
Solution Approach 2:
The NCO is designed to perform multiple functions including frequency synthesis and timing skew compensation. This multi-functionality approach allows the system to achieve accurate timing skew correction without adding dedicated correction hardware, thus reducing device complexity.
3Reliability
If high-performance timing skew correction is implemented, then ADC system performance is improved, but power consumption increases
Solution Approach 1:
The patent combines timing skew correction with the digital down-conversion process using the NCO. This integration ensures that high-performance correction is achieved without requiring separate power-hungry correction circuits, thereby improving ADC system performance while keeping power consumption low.
Solution Approach 2:
The NCO serves dual purposes of frequency synthesis and timing skew compensation, enabling the system to achieve high performance through a single low-power component rather than multiple specialized blocks, thus improving reliability without increasing power consumption.
4Measurement precision
If complex digital implementation is used for timing skew correction, then compensation accuracy is improved, but ease of manufacture decreases
Solution Approach 1:
The patent combines timing skew correction with the existing digital down-conversion block, utilizing the NCO for both functions. This merging simplifies the overall hardware architecture and makes the system easier to manufacture by reducing the number of discrete components while maintaining high compensation accuracy.
Solution Approach 2:
The NCO is designed to perform multiple functions including frequency synthesis and timing skew compensation. This multi-functionality reduces the overall system complexity and ease of manufacture by eliminating the need for separate correction circuits, while still achieving high compensation accuracy.
Data Source
AI summary
An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.