Analogue-Digital Converters TRIZ Cases

Reserved protocol bytes carry extra touch coordinate data, enabling floating-point sub-pixel resolution without changing the touchscreen interface.

A time-varying dither signal decorrelates ADC distortion in repetitive waveform digitization, enabling faster, higher-fidelity averaging.

Phase-domain NCO compensation inside the digital down-converter corrects timing skew in time-interleaved ADCs with low power and less hardware.

A time-interleaved DAC separates image frequencies so simpler anti-alias filtering can correct sub-DAC mismatch and DC offset errors.

Multiple lower-bandwidth ADCs use equalization to correct low-frequency path mismatches and preserve wideband sampling quality at lower cost.

Bit-level averaging of same-color pixel pairs cuts readout data volume and noise, improving image frame processing speed with lower power.

Programmable SAR delays and matrix-based correlation align interleaved ADC channels, cutting timing skew, spurious tones, and dynamic-range loss.

Analog voting suppresses dead and hot opaque-pixel outliers before row subtraction, cutting stripe noise and ADC burden in image sensors.

Digital up-counting and down-counting replace analog spike handling to reduce signal loss and improve neuron signal measurement accuracy.

Hardware background calibration updates ADC offsets from peak and trough pixel averages to speed fingerprint pickup and improve accuracy.

Pseudo-random dither and output correlation isolate non-linear kick-back in switched capacitor ADCs for accurate digital correction.

A phase-shifted reference ADC calibrates timing skew without pulling the main sampling network, cutting spurs and extra reference ADC area.

Delta encoding compresses multibit LIDAR ADC samples before transfer, cutting raw data traffic while preserving lossless full-waveform transmission.

Time-domain comparator interpolation converts direct RF input to digital codes without mixers, cutting hardware and power while preserving accuracy.

A reversible current mirror sets common-mode voltage with low quiescent current, improving reference-circuit stability and reducing thermal noise.

Multiple sampler outputs feed faster ADCs, using rate conversion and phase adjustment to simplify timing, component choice, and SNR.

Dual capacitor arrays use calibration voltage and differential references to correct mismatch, improving SAR ADC linearity with less circuit complexity.

Dynamic selection of N+2 sub-ADCs spreads mismatch errors into noise-like spectra, improving SFDR and reducing ranging errors.

Phase-domain NCO compensation corrects timing skew in time-interleaved ADCs with lower hardware complexity and power.

Real-time digital skew estimation and slope-based correction suppress TI-ADC spurs without hardware-heavy calibration or bandwidth loss.

Programmable calibration slots spread ADC foreground calibration across standby periods to preserve accuracy and limit power supply current modulation.

A folded current-mirror sampler separates gain from S11 matching to improve bandwidth, current scaling, and voltage headroom.

Multiple demodulators separate unique transmit frequencies so large touch sensors can keep high frame rates without losing noise immunity.

A unit-gain buffer isolates photodiode junction capacitance so ADC integration modules reset faster without losing sensing accuracy.

Dual avalanche photodiodes with processor-set bias balance photocurrents to reject laser RIN and improve LiDAR receiver SNR.

Phase-shifted clocks and PWM sampling let this ADC compute signal differences with linear operations, reducing complexity and resource use.

Adjusted ADC codewords realign TIADC sampling clocks to correct time skew, reducing distortion and improving SFDR.

Selective MDAC-stage test voltages check ADC degradation during idle time, cutting ASIL test overhead without extra reference circuits.

A static path masks transient artifacts while an adaptive path tunes gain and bandwidth to cut noise and power in analog front ends.

Two oscillator-based ADC paths compare input and reference signals to offset PVT variation and improve conversion speed, accuracy, and linearity.

Reception-count-based threshold switching filters solar noise in motor-scan LiDAR while avoiding long processing time, high power use, and added cost.

Integrating consecutive I/Q echo signals before ADC cuts UWB radar converter speed, power, and cost while improving noise suppression.

Three-level digital pulse generation replaces hand-tuned analog phase drives to cut harmonic content and simplify high-power transmission.

Edge-triggered channel switching and impedance sampling let a half-duplex re-driver bridge voltage domains without dedicated hubs or added bus loading.

Stage-by-stage adaptive foreground extraction quantifies capacitance mismatch, gain bandwidth, and kickback errors in pipeline ADCs without extra circuits.

Shared redundant sensor multiplexing cuts automotive temperature-sensing ADC count from 2N to N+1 while preserving ASIL-D checks.

Color-coded ternary patterns replace bulky binary scales, enabling precise optical length reading with fewer sensors and lower error risk.

Integrating consecutive I/Q echo signals before ADC cuts UWB radar digitization difficulty, power use, hardware cost, and noise.

Precomputed DAC calibration codes let a high-speed ADC correct nonlinearity with lookup-table access instead of complex real-time math.

A dual-comparator PRBS scheme estimates and corrects pipeline ADC gain and memory errors while tracking process, voltage, and temperature changes.

Embedding DEM and calibration inside the coarse ADC cuts propagation delay while correcting DAC and amplifier errors to improve SNR.

Voltage-stacking MDAC stages speed differential signal conversion while reducing comparator noise impact through passive gain and pipeline redundancy.

Switching sub-ADCs offline during operation enables calibration of offset, gain, and timing skew while preserving TI-ADC output quality.

Packet clocking and channel-level adaptive correction cut hardware complexity and stabilize bias, gain, and phase error correction in dense TI ADCs.

A delayed input path lets coarse and fine ADC stages run at maximum clock speed, raising sampling rate without added interleaving complexity.

Digital cross-correlation estimates CT ADC transfer functions while reducing test-signal leakage errors that degrade NSD and SNR.

High-frequency adaptive clocking and algorithmic denoising reduce noise-driven encoder sampling errors and improve motor control stability.

LSB digital enhancement adds an extra DAC resolution bit without more unit elements, cutting chip area and analog cell count.

Two attenuated ADC paths let one path switch gain while the other keeps converting, preserving signal quality across high dynamic range inputs.

Filtered ADC output trains a neural network to correct nonlinearity and PVT-driven distortion without extra calibration hardware.