Sub-Ranging ADC Timing With Delayed Input Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current sub-ranging analog-to-digital converters (ADCs) are limited by the need to reduce the ADC clock speed due to the sequential operation of coarse and fine ADCs, which restricts their ability to operate at maximum clock speeds afforded by semiconductor technology, thereby limiting sampling rates.
Innovation Solution
A non-blocking sub-ranging ADC system that uses a delay block to synchronize the operation of coarse and fine ADCs, allowing them to process signals simultaneously and operate at maximum clock speeds by delaying the input signal until the coarse ADC output is available, enabling the fine ADC to process the signal as soon as it is ready.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential operation of coarse and fine ADCs is used, then resolution is improved, but sampling rate is reduced
Solution Approach 1:
The coarse ADC performs its conversion operation in advance before the fine ADC operates. The delay block holds the input signal until the coarse ADC completes its conversion, ensuring the fine ADC receives both the delayed signal and coarse ADC output simultaneously. This preliminary action by the coarse ADC enables subsequent fine conversion without blocking the overall timing.
Solution Approach 2:
The delay block acts as an intermediary element that mediates between the input signal and the fine ADC. It delays the input signal to synchronize with the coarse ADC operation, allowing both ADCs to operate in a coordinated manner that achieves high resolution while maintaining high sampling rates through proper timing alignment.
2Reliability
If ADC clock speed is reduced to maintain signal validity, then operation reliability is improved, but productivity deteriorates
Solution Approach 1:
The coarse ADC completes its conversion operation in advance, and the delay block holds the input signal until this conversion is complete. This preliminary action ensures that when the fine ADC operates, both the delayed input signal and coarse ADC output are simultaneously available, eliminating the need to reduce clock speed to maintain signal validity.
Solution Approach 2:
The system dynamically adjusts the timing of signal processing through the delay block, which adapts the signal timing to match the coarse ADC conversion completion. This dynamic timing adjustment allows the fine ADC to operate at maximum clock speed while ensuring reliable operation by synchronizing with the coarse ADC output availability.
3Productivity
If multiple T/H, CADC, and FADC blocks are used in interleaved fashion, then sampling rate is improved, but device complexity increases
Solution Approach 1:
The coarse ADC performs its conversion operation in advance before the fine ADC operates. The delay block holds the input signal until the coarse ADC completes its conversion, ensuring the fine ADC receives both the delayed signal and coarse ADC output simultaneously. This preliminary action by the coarse ADC enables subsequent fine conversion without blocking the overall timing.
Solution Approach 2:
The system maintains continuous operation by having the coarse ADC and fine ADC work in a coordinated sequence without idle time. The delay block ensures the input signal is held ready, and both ADCs operate continuously at their maximum clock speeds, achieving high sampling rates without requiring multiple interleaved ADC blocks that would increase complexity.
Data Source
AI summary
Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.