Pipelined ADC Voltage Stacking for Faster Low-Noise Conversion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current SAR ADC-based approaches in high-speed SerDes links are bottlenecked by the need for multiple clock cycles to determine digital representation of analog signals, with comparator noise limiting noise performance and previous designs like hybrid SAR/pipeline architectures being limited by SAR stages that reduce conversion rate.
Innovation Solution
A pipelined ADC circuit with multiple stages, each with differential input and MDAC for voltage stacking, a comparator for decision-making, and a source follower buffer for amplification, allowing for high-speed conversion with reduced noise impact and error correction through redundancy in the radix system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If SAR ADC-based approaches are used for high-speed SerDes links, then digital representation of analog signals can be achieved, but conversion rate is limited due to need for multiple clock cycles
Solution Approach 1:
The ADC conversion process is divided into multiple independent pipeline stages, where each stage performs a portion of the conversion in parallel. This segmentation allows the system to achieve high conversion rates by processing multiple bits simultaneously across stages rather than sequentially in a single SAR ADC.
Solution Approach 2:
The pipeline ADC employs dynamic element matching and time-interleaved architectures that dynamically allocate resources across clock cycles. This dynamic operation enables the system to maintain high conversion rates while managing the complexity of multiple clock cycles through adaptive resource utilization.
2Measurement precision
If comparator noise is present in SAR ADC, then digital conversion can proceed, but noise performance is limited
Solution Approach 1:
The conversion process is segmented into multiple stages, each with its own comparator. By dividing the total conversion into stages, the noise from individual comparators affects only a portion of the total conversion, and subsequent stages can correct for this noise through their own comparison operations, thereby improving overall noise performance.
Solution Approach 2:
The pipeline architecture incorporates feedback mechanisms where the output of each stage is fed forward to subsequent stages. This feedback allows later stages to compensate for noise and errors introduced by earlier comparators, improving the overall signal-to-noise ratio and measurement precision.
3Productivity
If hybrid SAR/pipeline architectures are used, then conversion rate can be improved, but SAR stages reduce the conversion rate
Solution Approach 1:
The hybrid architecture is segmented into SAR stages and pipeline stages, where each type performs its specialized function. The SAR stages handle coarse conversion while pipeline stages handle fine conversion, allowing the system to achieve high conversion rates without requiring all stages to operate at the full SAR conversion speed.
Solution Approach 2:
Different stages of the converter are given different local qualities - SAR stages are optimized for coarse conversion with lower speed requirements, while pipeline stages are optimized for high-speed fine conversion. This local optimization allows each stage to operate at its optimal speed, improving overall conversion rate without requiring all stages to be high-speed SAR stages.
Data Source
AI summary
Systems and methods are provided for a pipelined analog-to-digital converter (ADC) circuit. The pipelined ADC circuit comprises a plurality of stages. Each stage comprises a differential input configured to receive a differential signal, a multiplying digital-to-analog converter (MDAC) electrically coupled to the input configured to stack voltages of a set of capacitors; a comparator electrically disposed after the MDAC to compare the differential voltages; and a source follower buffer electrically coupled to the first signal line and the second signal line and electrically disposed after the comparator, wherein the MDAC is configured to amplify an output voltage using passive multiplication; and an alignment circuit communicatively connected to a digital bit output of each stage of the plurality of stages, wherein the alignment circuit is configured to delay a digital bit output of each stage for one or more clock cycles and output a digitized representation of a sampled differential signal.