Time-Interleaved ADC Architecture With Flexible Sample-Rate Matching
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Solution Overview
Problem
Traditional time-interleaved analog-to-digital converters are complex and difficult to design, limiting the choice of components and hindering flexibility due to the requirement of matching sample rates between samplers and analog-to-digital converters.
Innovation Solution
An analog-to-digital converter system with a sampler generating multiple output signals at a predetermined output sample rate and phase shift, and analog-to-digital converters operating at a higher converter sample rate than the output sample rate, allowing for the use of any sampler with any analog-to-digital converter having a higher sample rate, and a signal processor for rate modification and phase adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional time-interleaved A/D-converters are used to achieve high sample rates, then the sample rate is improved, but the device complexity increases and design becomes difficult
Solution Approach 1:
The system divides the high-speed sampling task into multiple parallel A/D converters operating at lower individual sample rates. Each converter processes a portion of the time-interleaved input signals, and their outputs are combined to achieve the overall high sample rate. This segmentation reduces the complexity of each individual converter while maintaining the high overall sample rate capability.
Solution Approach 2:
Multiple A/D converters are merged into a single time-interleaved system where their outputs are combined through a signal processor. The individual converter outputs are interleaved in time to form the final high-rate digital signal, effectively merging the capabilities of multiple lower-rate converters to achieve high sample rate performance.
2Reliability
If sample rates of sampler and analog-to-digital converters are matched exactly as in traditional systems, then timing synchronization is improved, but component selection is limited and flexibility is reduced
Solution Approach 1:
The system employs dynamic resampling and phase adjustment mechanisms that allow the A/D converters to operate at fixed sample rates independent of the sampler output rate. The signal processor dynamically adjusts the timing and phase of converter outputs to achieve proper synchronization, enabling flexible component selection while maintaining timing accuracy.
Solution Approach 2:
The system changes the sampling parameter relationship by allowing A/D converters to operate at different sample rates than the sampler output. Instead of requiring exact matching, the system uses digital signal processing to adjust the effective sampling rate and phase, providing flexibility in component selection while maintaining synchronization through parameter transformation.
3Ease of manufacture
If standard components are used with different sample rates, then component availability and cost are improved, but signal processing complexity increases
Solution Approach 1:
A signal processor acts as an intermediary between the sampler and A/D converters, handling the complexity of rate mismatch and phase alignment. This mediator performs resampling, phase adjustment, and signal combination operations, isolating the complexity from the individual components and allowing them to be selected independently based on availability and cost considerations.
Data Source
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AI summary
The present disclosure provides an analog-to-digital converter system (100, 200) comprising a sampler (101, 201) configured to sample an input signal (103, 203, 403) and provide at least two output signals (105-1, 105-n, 205-1, 205-n, 305, 505, 405-1, 405-2, 605, 905, 1005) with a predetermined output sample rate, and an analog-to-digital converter (106-1, 106-n, 206-1, 206-n, 306) for each one of the output signals (105-1, 105-n, 205-1, 205-n, 305, 505, 405-1, 405-2, 605, 905, 1005) and configured to convert the respective output signal (105-1, 105-n, 205-1, 205-n, 305, 505, 405-1, 405-2, 605, 905, 1005) into a digital signal (107-1, 107-n) with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate. Further, the present disclosure provides a respective method.