Packet-Clocked TI ADC Correction for Bias, Gain, and Phase Errors
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Solution Overview
Problem
Traditional error estimation and correction technologies for time-interleaved analog-to-digital converters (TI ADCs) face challenges with increasing channel integration, leading to high hardware complexity and reduced stability, making accurate correction difficult, especially in dense channel integration scenarios.
Innovation Solution
An error compensation correction system and method that includes a master clock module, packet clock module, error correction module, adaptive processing module, and overall MUX circuit, which packet sub-ADCs and use packet clock modules to generate and synchronize operation clocks, correct bias, gain, and clock phase errors, and synthesize corrected data, reducing hardware complexity and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional error correction technology is used with increasing number of TI ADC channels, then measurement precision is improved, but device complexity increases significantly
Solution Approach 1:
The patent segments the TI ADC system into multiple independent sub-ADC channels, each with its own error correction processing. By dividing the error correction task into channel-specific segments rather than processing all channels through a single complex system, the hardware complexity is reduced while maintaining correction precision for each channel independently
Solution Approach 2:
The patent performs preliminary error correction processing within each sub-ADC channel before the signals are combined. By pre-correcting bias, gain, and clock phase errors at the channel level before multiplication and summation, the system avoids the need for complex post-processing of the combined signal, thereby reducing overall device complexity
2Productivity
If more channels are integrated in TI ADC, then productivity is improved, but reliability decreases due to mutual influence of estimation results
Solution Approach 1:
The patent divides the TI ADC into multiple independent sub-ADC channels, each processing signals independently with separate error estimation and correction. This segmentation prevents mutual interference between channels during error estimation, improving reliability while maintaining high productivity through parallel processing of multiple channels
Solution Approach 2:
The patent applies local error correction processing to each sub-ADC channel individually, allowing each channel to have optimized correction parameters adapted to its specific characteristics. This localized approach prevents errors in one channel from affecting the estimation accuracy of other channels, thereby improving overall system reliability
3Measurement precision
If more sample points are used for estimation in dense channel integration, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary error estimation and correction within each sub-ADC channel using a limited number of sample points. By completing the essential error correction before the full signal processing chain, the system achieves good estimation accuracy without requiring excessive sample points, thus reducing convergence time
Solution Approach 2:
The patent applies partial correction processing to each channel individually rather than processing all channels simultaneously with full sample sets. This partial action approach achieves sufficient estimation accuracy for each channel using fewer sample points, reducing the total time required for convergence across the entire TI ADC system
Data Source
AI summary
The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.