Pipeline ADC Self-Test Circuitry for MDAC Stage Degradation
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Solution Overview
Problem
Current RADAR systems with pipeline ADC circuitry face significant hardware and cost overhead due to extensive testing requirements for ASIL compliance, particularly in automotive applications, which involve numerous input samplings and complex parameter checks like DNL, INL, and FFT tests.
Innovation Solution
The implementation of ADC testing circuitry that uses selective few input combinations to detect performance degradation in MDAC stages, specifically designed to identify errors caused by small signal parameter changes, such as gain errors and capacitive value changes, without requiring additional reference voltage generation circuits or extensive input sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If extensive testing implementations (DNL, INL, FFT tests) are used to check ADC performance, then measurement precision and reliability are improved, but device complexity and manufacturing cost increase substantially
Solution Approach 1:
The patent extracts only the essential testing functionality needed for ASIL compliance by implementing a simplified test mode that selectively activates specific test circuits within the ADC architecture. This allows extraction of critical performance checking capabilities while eliminating redundant testing hardware, thereby reducing device complexity while maintaining measurement precision for safety-critical parameters.
Solution Approach 2:
The testing approach is segmented into different operational modes (normal operation mode and test mode) with dedicated test circuits activated only when needed. The test functionality is divided into specific test cases (e.g., DNL test, INL test) that can be independently activated, allowing the system to maintain high measurement precision for critical parameters while avoiding the complexity of running all tests simultaneously or continuously.
2Reliability
If comprehensive ADC parameter testing is implemented, then reliability for ASIL requirements is improved, but hardware overhead and manufacturing cost increase
Solution Approach 1:
The patent implements multi-functional test circuits that can perform multiple testing functions using shared hardware resources. The same test circuitry is used across different ADC channels and can execute various test types (DNL, INL, FFT) through software control, eliminating the need for dedicated hardware for each test type. This universal approach maintains ASIL compliance reliability while significantly reducing hardware overhead and manufacturing cost.
Solution Approach 2:
The ADC system performs self-testing by incorporating test functionality directly into the existing ADC architecture without requiring external testing equipment. The test mode utilizes the ADC's own internal resources (converters, comparators, capacitors) to generate test signals and evaluate performance, enabling the system to self-verify ASIL compliance while minimizing additional hardware requirements.
3Measurement precision
If many input samples are taken for testing, then measurement precision is improved, but time overhead increases substantially
Solution Approach 1:
The patent implements periodic testing where comprehensive ADC parameter measurements are performed at scheduled intervals rather than continuously. During normal operation, the ADC processes real-time signals, and testing is activated periodically to verify performance parameters. This periodic approach maintains measurement precision for safety-critical parameters while minimizing time overhead by avoiding continuous testing.
Solution Approach 2:
The system performs preliminary characterization during manufacturing to establish baseline performance parameters, then uses these pre-established references for ongoing compliance verification. This preliminary action allows the system to maintain high measurement precision by comparing against known good references while reducing the number of samples needed during operational testing, thereby minimizing time overhead.
Data Source
AI summary
A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.