Pipeline ADC Stochastic Comparator for Gain and Memory Error Estimation
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Solution Overview
Problem
Analog front-end (AFE) circuits, particularly in pipeline analog-to-digital converters (ADCs), face challenges due to gain errors and memory issues caused by amplifiers, leading to performance degradation and high power consumption.
Innovation Solution
The implementation of a stochastic comparator with two comparators and a pseudo random binary sequence (PRBS) signal, along with a XOR gate, allows for improved estimation and correction of gain and memory errors, enabling accurate digital output while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an amplifier is used in the ADC for amplifying signals, then the ADC can process weak analog signals, but gain error is introduced which degrades ADC performance
Solution Approach 1:
The patent implements a feedback mechanism where the digital output of the ADC is converted back to analog form and compared with the original analog input signal. The difference between these signals is used to generate correction signals that compensate for gain errors in the amplifier, thereby maintaining measurement precision while allowing signal amplification.
Solution Approach 2:
The patent introduces an intermediary correction signal generation mechanism that mediates between the amplified signal path and the digital output. This intermediary system processes the difference between the original and reconstructed signals to create corrective adjustments, isolating the gain error effects from the main signal path.
2Speed
If the amplifier operates at high speed, then the ADC can process high frequency signals, but memory effects occur which hinder accurate digital output generation
Solution Approach 1:
The feedback mechanism continuously monitors the difference between the original analog input and the reconstructed analog signal from digital output. This feedback loop captures memory effects introduced by high-speed amplifier operation and generates correction signals that compensate for these effects in real-time, maintaining digital output accuracy at high processing speeds.
Solution Approach 2:
The correction signal generation operates continuously alongside the main ADC conversion process. The system continuously processes the difference signal to generate corrective adjustments, ensuring that memory effects are compensated throughout the entire high-speed operation rather than requiring separate calibration phases.
3Device complexity
If a traditional single comparator is used in the ADC, then the device complexity is low, but the ability to detect and estimate gain and memory errors is insufficient
Solution Approach 1:
The patent segments the error detection function into distinct operational phases: a first phase where comparators operate with normal input signals to perform conversion, and a second phase where comparators operate with test signals to estimate gain and memory errors. This segmentation allows the same hardware to perform both conversion and error characterization without requiring additional dedicated error detection circuits.
Solution Approach 2:
The comparator circuit is designed to perform multiple functions: normal analog-to-digital conversion during the first phase and gain/memory error estimation during the second phase. This multi-functionality eliminates the need for separate dedicated error detection hardware, maintaining low device complexity while enhancing error detection capability.
4Productivity
If the ADC operates continuously without error correction, then the productivity is high, but the digital output accuracy degrades due to accumulated gain and memory errors
Solution Approach 1:
The patent implements periodic error estimation phases interspersed with normal conversion operations. During these periodic intervals, the system switches to test signal mode to estimate gain and memory errors, then applies these corrections to subsequent conversions. This periodic approach maintains high productivity by minimizing the time spent in correction mode while ensuring accuracy through regular error characterization and correction.
Data Source
AI summary
In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.