Pipeline ADC Dynamic Element Matching for Low-Latency Error Correction
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Solution Overview
Problem
Pipeline analog-to-digital converters face limitations in performance and speed due to errors in digital-to-analog converters (DAC) and amplifiers, as well as excessive delay, which degrade linearity and signal-to-noise ratio (SNR), especially at high clock rates.
Innovation Solution
Embedding Dynamic Element Matching (DEM) and Harmonic Distortion Correction (HDC) functions within the circuitry of a coarse ADC and rearranging digital calibration blocks to accurately estimate and correct DAC and amplifier errors, minimizing propagation time and increasing DAC resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Dynamic Element Matching (DEM) and Harmonic Distortion Correction (HDC) functions are embedded within the coarse ADC circuitry, then error correction accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the DEM and HDC functions with the coarse ADC circuitry by integrating the permutation matrix generation and harmonic distortion correction logic directly into the ADC structure. This consolidation allows error correction to occur within the existing signal path without requiring separate external processing stages, thereby improving correction accuracy while managing complexity through unified design.
Solution Approach 2:
The coarse ADC circuitry is designed to perform multiple functions: analog-to-digital conversion, dynamic element matching through permutation matrix application, and harmonic distortion correction. By making the circuit multi-functional, the patent eliminates the need for separate dedicated circuits for each function, addressing the complexity concern while maintaining high error correction accuracy.
2Measurement precision
If DEM block is placed between coarse ADC and DAC, then DAC errors are randomized and SNR is improved, but propagation delay increases
Solution Approach 1:
The patent applies the permutation matrix and performs element matching operations before the signal reaches the DAC stage. By conducting the DEM processing in advance within the coarse ADC circuitry, the signal is pre-conditioned with error randomization already applied, eliminating the need for additional delay-inducing processing stages after the ADC and thereby reducing overall propagation delay while maintaining SNR improvement.
3Measurement precision
If DAC resolution is increased, then quantization accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and addresses the sources of quantization error (DAC element mismatches and harmonic distortions) separately through DEM and HDC techniques applied to the coarse ADC output. By correcting these errors before they propagate to the final conversion stage, the system achieves high quantization accuracy without requiring the DAC itself to have extremely high resolution, thereby reducing DAC complexity and manufacturing cost.
Data Source
Figure 1A~1B
Figure 2
Figure 3~4
AI summary
A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.