Pipeline ADC Foreground Error Extraction Without Extra Circuits
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Solution Overview
Problem
Traditional pipeline analog-to-digital converters face challenges in accurately quantifying and correcting capacitance mismatch, gain bandwidth, and kickback errors, particularly at high speeds, due to the need for additional circuits and complex digital algorithms, which complicates OTA design and increases power consumption.
Innovation Solution
An error extraction method for foreground digital correction that involves acquiring a transmission curve, controlling input signals, locking comparator outputs, and using sequential adaptive iteration to extract errors stage-by-stage, without requiring additional circuits, through formulas for capacitance mismatch, gain error, and kickback error extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional pipeline ADC foreground correction is used to extract capacitance mismatch error and gain bandwidth error of the first stage by INL measurement, then correction of first stage errors is achieved, but correction of later stages is not performed and additional circuits are required for complete correction
Solution Approach 1:
The patent segments the error extraction process by stage, using a segmented error extraction value that corresponds to each pipeline stage. This allows independent extraction and correction of errors from each stage without requiring additional circuits for each stage, thereby maintaining measurement precision while reducing device complexity
Solution Approach 2:
The patent creates a universal correction approach that can correct errors from multiple stages simultaneously through a single correction circuit. The segmented error extraction values from different stages are combined into a unified correction value that can be applied by one correction circuit, achieving multi-stage correction without proportionally increasing circuit complexity
2Productivity
If pipeline ADC operates at higher speeds, then productivity is improved, but kickback error increases and requires additional digital correction
Solution Approach 1:
The patent extracts kickback error values during the normal conversion process without requiring separate correction cycles or additional time margins. The kickback error is captured and corrected in the same operational flow, allowing high-speed operation without sacrificing accuracy or requiring extra time for correction
Solution Approach 2:
The correction circuit uses the inherent operational characteristics of the ADC stages to self-identify and correct kickback errors. By utilizing the natural signal flow and comparator outputs during normal operation, the system corrects its own errors without external intervention or additional correction mechanisms
3Reliability
If digital correction is applied to multiple pipelined stages, then correction comprehensiveness is improved, but calculation complexity increases
Solution Approach 1:
The patent changes the parameter representation by using segmented error extraction values that simplify the mathematical relationships between stages. This parameter transformation reduces the complexity of combining errors from multiple stages, allowing comprehensive correction through simpler calculations rather than complex multi-stage algorithms
Data Source
AI summary
An error extraction method for foreground digital correction of a pipeline analog-to-digital converter including: acquiring a transmission curve of a pipeline analog-to-digital converter, and controlling an input signal to be within a sub-segment 0 of the transmission curve; during extraction of error information of an ith pipeline stage, setting a magnitude of the input signal according to Formula (I); locking the outputs of all previous-stage comparators in the ith pipeline stage of the pipeline analog-to-digital converter; and completing, according to original output code of the pipeline analog-to-digital converter, error extraction by means of adaptive iteration, stage-by-stage, sequentially from a last stage to a first stage of a pipeline. During quantization of error value, the invention performs, by means of a fitting-based adaptive algorithm, foreground extraction of a capacitance mismatch error, a gain bandwidth error, and a kickback error in each stage of the pipeline, without any additional circuit.