Interleaved ADC Timing Calibration Using SAR Delay Matrix Processing
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Solution Overview
Problem
Interleaved Analog-to-Digital Converters (ADCs) face challenges in achieving high sampling rates due to timing skews and mismatches between channels, leading to spurious tones and reduced dynamic range, particularly when multiple channels are interleaved, necessitating a calibration method to introduce programmable delays and minimize timing skews.
Innovation Solution
The implementation of a calibration system using product derivative correlators and a matrix processor to adjust programmable input delays in a Successive-Approximation-Register (SAR) delay element, which compensates for timing skews by testing various delay values and storing them in binary-weighted capacitor elements, thereby reducing sampling pulse-width and component mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ADC channels are interleaved together to achieve higher sampling rates, then the sampling rate increases, but timing skews and mismatches between channels introduce spurious tones and reduce dynamic range
Solution Approach 1:
The patent applies parameter changes by introducing variable delay elements that can adjust the timing parameters of each channel. The delay elements modify the time delay parameter for each ADC channel individually, allowing the system to compensate for timing skews and mismatches while maintaining high sampling rates achieved through interleaving multiple channels.
2Measurement precision
If variable delays are introduced to each channel to correct timing skews, then timing accuracy improves, but device complexity increases due to additional delay elements and calibration requirements
Solution Approach 1:
The patent implements self-service through an automated calibration system that performs background calibration without requiring external intervention. The calibration process automatically measures timing skews between channels and adjusts the delay elements accordingly, enabling the system to self-correct timing inaccuracies while operating. This reduces the operational complexity despite the added hardware for calibration.
Solution Approach 2:
The calibration system employs feedback mechanisms where the measured timing skew information is fed back to adjust the delay elements. The system continuously monitors timing differences between interleaved channels and uses this feedback to optimize the delay settings, achieving accurate timing synchronization while managing complexity through systematic feedback control.
3Stability of the object's composition
If background calibration is performed to adjust for gradual temperature skews, then long-term stability improves, but processing time and computational resources are consumed
Solution Approach 1:
The patent implements periodic action through background calibration that operates at predetermined intervals rather than continuously. The calibration process is triggered periodically to adjust for gradual temperature-induced timing skews, balancing the need for long-term stability with the consumption of processing time. This periodic approach maintains timing accuracy over temperature variations while minimizing the time and computational resources dedicated to calibration.
Data Source
AI summary
An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.