Differential ADC Using Phase-Shifted Sampling and Linear Processing
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Solution Overview
Problem
There is a growing need for a highly accurate and efficient analog to digital converter that can effectively convert analog signals to digital signals, with existing solutions often requiring complex operations and high resource consumption.
Innovation Solution
The proposed analog to digital converter includes a signal generator that produces phase-shifted clock signals and PWM-related signals, a processing unit that generates virtual counter and phase values, and a method that determines the difference between input signals using linear operations, avoiding modulo operations and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex operations and high resource consumption methods are used for analog to digital conversion, then measurement precision may be improved, but device complexity and computational resource consumption increase
Solution Approach 1:
The patent replaces complex computational operations (modulo operations) with simpler linear operations in the digital processing stage. The analog-to-digital conversion uses linear summation of phase-shifted samples instead of requiring complex modulo arithmetic, significantly reducing computational complexity while maintaining conversion accuracy.
Solution Approach 2:
The patent transforms the conversion process by changing the mathematical parameters from non-linear modulo operations to linear operations. By using phase-shifted clock signals and linear combination of samples, the system achieves accurate conversion without the computational burden of traditional methods.
2Measurement precision
If complex operations are used for analog to digital conversion, then measurement precision may be improved, but computational resource consumption increases
Solution Approach 1:
The patent substitutes energy-intensive modulo operations with low-power linear operations. The digital processing unit performs simple addition and subtraction of phase-shifted sample values, consuming significantly less computational energy while achieving the same conversion accuracy as complex methods.
3Reliability
If traditional conversion methods are used, then reliability may be maintained, but device complexity increases
Solution Approach 1:
The patent segments the conversion process into distinct phases: analog sampling with phase-shifted clock signals, digital processing with linear operations, and output generation. This segmentation allows each stage to be optimized independently, maintaining reliability while reducing overall operational complexity through specialized simple operations in each segment.
Data Source
AI summary
An analog to digital converter (ADC) that may include an input configured to receive a first signal and a second signal; a signal generator that is configured to generate multiple signals, the multiple signals may include a phase-shifted clock signals that are phase shifted from each other, first pulse width modulation (PWM) related signals indicative of a value of the first signal, second PWM related signals indicative of a value of the second signals, a first sampled stream, a second stream that have substantially opposite phases, and phase related signals related to the first sampled stream and the second sampled stream; wherein the first sampled stream and the second sampled stream are generated based on at least one of the phase shifted clock signals; and a processing unit that is configured to receive at least some of the multiple signals, the at least some of the multiple signals may include the first PWM related signals, the second PWM related signals, and the phase related signals; generate, based on the at least some of the multiple samples, virtual counter values and virtual phase values that are mutually aligned; determine a value of a difference between the first signal and the second signal, and output an ADC output signal indicative of the difference between the first signal and the second signal.