Time-Interleaved ADC Calibration for Mismatch Compensation
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Solution Overview
Problem
Time-Interleaved Analog-to-Digital Converter (TI-ADC) systems face performance degradation due to mismatches such as DC offset, gain, and timing skew among sub-ADCs, which are challenging to calibrate, especially in applications like 3GPP base station receivers where high accuracy and low noise Power Spectral Density (nPSD) and large Spurious Free Dynamic Range (SFDR) are required, particularly in FDD modes where offline calibration is not feasible.
Innovation Solution
A TI-ADC system with a switching circuit that allows either or both ADC circuits to be taken offline for calibration, using a parameter determination circuit to generate correction parameters for mismatches, and an output circuit to produce a digital output signal based on the corrected signals from both ADCs, enabling calibration schemes that compensate for multiple mismatches simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If offline calibration is performed to achieve high accuracy, then measurement precision is improved, but productivity is worsened due to system downtime
Solution Approach 1:
The patent implements preliminary calibration actions by storing correction parameters in a lookup table that is pre-computed and stored offline. During operation, the system performs rapid lookup and application of these pre-determined correction parameters, achieving high precision without requiring the system to go offline for calibration.
Solution Approach 2:
The patent dynamically adjusts correction parameters based on operating conditions. The system selects appropriate correction parameters from the lookup table based on current operating modes (e.g., different bandwidths, sampling rates), allowing the calibration to adapt to changing conditions without requiring re-calibration or system shutdown.
2Measurement precision
If multiple correction parameters are applied to compensate for mismatches, then measurement precision is improved, but device complexity is worsened
Solution Approach 1:
The patent merges multiple correction operations into a single lookup table structure that stores pre-computed correction parameters for all mismatch types (DC offset, gain, timing skew, frequency response). Instead of implementing separate correction circuits for each mismatch type, the system combines them all into one unified lookup table that can be queried to obtain all necessary corrections simultaneously.
Solution Approach 2:
The patent uses a digital copy (lookup table) to store correction parameters instead of implementing complex analog correction circuits. The lookup table contains pre-computed digital representations of all necessary corrections, which are then applied through simple digital processing, replacing complex hardware with simpler software-based solutions.
3Speed
If lookup tables are used for rapid correction parameter access, then speed is improved, but device complexity is worsened due to memory requirements
Solution Approach 1:
The patent segments the lookup table into multiple smaller tables organized hierarchically. The lookup structure is divided into different levels or segments that can be accessed in sequence, reducing the complexity of any single table while maintaining fast access performance. This segmentation also allows for more efficient memory management and caching strategies.
Data Source
AI summary
A time-interleaved Analog-to-Digital Converter, ADC, system is provided. The time-inter-leaved ADC system includes time-interleaved first and second ADC circuits and a switching circuit. The switching circuit is configured to selectively supply an analog input signal for digitization to at least one of the first ADC circuit, the second ADC circuit or ground, and to selectively supply an analog calibration signal to at least one of the first ADC circuit, the second ADC circuit or ground. Further, the time-interleaved ADC system includes an output circuit configured to selectively generate, based on least one of a first digital signal output by the first ADC circuit and a second digital signal output by the second ADC circuit, a digital output signal.