Time-Interleaved ADC Timing Skew Correction in Digital Down Conversion
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face significant performance issues due to timing skew errors, which are challenging to accurately compensate using existing techniques, especially in high-performance ADCs, as traditional methods require complex hardware and high power consumption or are not effective for signals with repeated patterns or changing statistics.
Innovation Solution
The integration of a timing skew correction function within the signal down-conversion block using a numerically controlled oscillator (NCO) allows for accurate compensation of timing offsets with minimal power penalty, employing a small angle approximation for dynamic updates and discrete Fourier transform-based phase error estimation to correct timing skew errors in the digital domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional timing skew compensation methods are used, then timing accuracy may be improved, but hardware complexity and power consumption increase significantly
Solution Approach 1:
The patent replaces complex analog timing skew compensation hardware with digital signal processing methods. Specifically, it uses discrete Fourier transform-based phase error estimation and numerically controlled oscillator (NCO) phase adjustment to compensate timing skew in the digital domain, eliminating the need for complex analog delay lines and phase shifters while maintaining high timing accuracy
Solution Approach 2:
The patent creates a digital model of the timing skew error through phase error estimation using discrete Fourier transform. By analyzing the spectral components of the ADC output and estimating the phase deviation caused by timing skew, the system creates a digital representation of the error that can be compensated through NCO phase adjustment without requiring physical hardware copies of the timing correction mechanism
2Measurement precision
If additional digital blocks are added for timing skew correction, then timing accuracy improves, but power consumption increases
Solution Approach 1:
The patent integrates the timing skew compensation function into the existing NCO block that is already part of the digital down-conversion architecture. The NCO serves dual purposes: frequency synthesis for down-conversion and timing skew compensation through phase adjustment. This multi-functionality eliminates the need for separate dedicated timing correction hardware, thereby avoiding additional power consumption while achieving high timing accuracy
Solution Approach 2:
The patent merges the timing skew compensation function with the digital down-conversion process. By combining the phase error estimation and NCO-based compensation into the existing signal processing chain, the system achieves timing correction without adding separate power-consuming digital blocks. The compensation is performed as an integrated part of the normal signal processing operations
3Device complexity
If analog-domain timing correction is used, then implementation is simpler, but tuning resolution is limited
Solution Approach 1:
The patent replaces analog timing correction mechanisms with digital phase adjustment using NCO. Instead of using analog delay lines or variable phase shifters with limited resolution, the system uses digital phase word adjustment in the NCO, which provides fine-grained control over the phase compensation. This digital approach maintains implementation simplicity while dramatically improving tuning resolution through the high-resolution phase accumulator of the NCO
Data Source
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Figure 3A~3B
AI summary
An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.