TIADC Sampling Clock Correction for Time-Skew Mismatch

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Solution Overview

Problem

In time-interleaved analog-to-digital converters (TIADCs), sampling time-period mismatches between ADCs lead to waveform distortion and reduced spurious-free dynamic range (SFDR) due to inconsistent sampling time skews, necessitating an effective method to adjust these skews.

Innovation Solution

An error correction method that adjusts codewords corresponding to ADCs, using an error estimation circuit and clock frequency division circuit to generate sampling clocks, ensuring the sampling time-period skew is aligned with a preset range, thereby correcting the sampling time-period mismatch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple ADCs perform sampling in time-interleaved manner, then sampling rate is improved, but sampling time-period skew between ADCs deteriorates SFDR

Engineering Contradiction:
Improvesampling rateVSAvoidSFDR
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the skew detection unit continuously monitors the time-period skew between adjacent ADCs and feeds this information to the skew correction unit. This closed-loop feedback system dynamically adjusts the sampling time periods to maintain optimal SFDR while preserving the high sampling rate benefits of time-interleaved architecture.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the sampling time period parameters of individual ADCs based on detected skew conditions. The skew correction unit modifies the time period of at least one ADC's sampling clock to compensate for mismatches, thereby maintaining consistent sampling intervals across all ADCs and improving SFDR without reducing the overall sampling rate.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If sampling time-period skew between ADCs is not adjusted, then device complexity is reduced, but waveform distortion increases

Engineering Contradiction:
Improvesystem complexityVSAvoidwaveform accuracy
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent introduces intermediary components (skew detection unit and skew correction unit) that mediate between the multiple ADCs to detect and correct time-period skews. These intermediaries manage the complexity by providing a systematic approach to skew correction, preventing waveform distortion while maintaining relatively simple individual ADC designs.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If codewords are adjusted to correct skew, then sampling time-period alignment is improved, but device complexity increases

Engineering Contradiction:
Improvetime-period alignmentVSAvoidcontrol circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the skew correction function into distinct modular units: a skew detection unit that measures time-period deviations and a skew correction unit that generates corrected codewords. This segmentation allows for independent optimization of each function and simplifies the overall control logic by dividing the correction task into manageable stages rather than requiring a monolithic complex controller.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11476861B2Error correction method and time-interleaved analog-to-digital converter
Publication Date: 2022.10.18 HUAWEI TECH CO LTD
  • US11476861B2 patent drawing
  • US11476861B2 patent drawing
  • US11476861B2 patent drawing

AI summary

An error correction method and a time-interleaved analog-to-digital converter (TIADC) are provided. The method is applied to a TIADC that includes a plurality of analog-to-digital converters (ADCs), and the method includes: determining whether a current value of a codeword of a first ADC in the plurality of ADCs is within a preset range; when the current value of the codeword of the first ADC is not within the preset range, adjusting a plurality of codewords that are in a one-to-one correspondence with the plurality of ADCs; and controlling a clock frequency division circuit to generate, by using a plurality of adjusted codewords, a plurality of sampling clocks that are in a one-to-one correspondence with the plurality of ADCs. In embodiments of this application, a sampling time-period skew existing between ADCs may be adjusted by adjusting codewords corresponding to the ADCs.