ADC Early Interrupt Pipeline for Shorter PID Control Latency
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Solution Overview
Problem
Control system stability is compromised by delays in analog-to-digital signal conversion and information transfer, leading to overshoot and instability, particularly in high-performance electronic control devices, due to the high cost and power consumption of faster digital processors and ADCs.
Innovation Solution
An apparatus with a digital processor, interrupt controller, pipelined ADC, and pipelined registers that allow for early interrupts during analog-to-digital conversion, reducing delay times by overlapping processor overhead with ADC conversion completion, using a circuit to select pipelined registers for consistent delay times and enabling interrupts before conversion completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If faster digital processors and ADCs are used to reduce control loop delays, then control loop stability and response time are improved, but cost and power consumption increase
Solution Approach 1:
The patent implements early interrupt capability that allows the interrupt controller to be notified of conversion completion before the ADC actually finishes. This preliminary notification enables the digital processor to start preparing for the interrupt handling in advance, effectively reducing the perceived delay without requiring faster conversion hardware.
Solution Approach 2:
The patent divides the conversion completion notification process into separate stages by introducing pipelined registers that track conversion progress through multiple stages. Each register stage can be independently selected to provide different delay characteristics, allowing the system to optimize between speed and power consumption based on specific needs.
2Loss of time
If faster digital processors and ADCs are used to reduce control loop delays, then control loop stability is improved, but cost increases
Solution Approach 1:
The early interrupt capability allows the system to prepare for interrupt handling in advance of the actual conversion completion, reducing the effective delay without requiring more expensive high-speed ADC hardware. The pipelined structure enables this preparation to occur concurrently with the conversion process.
Solution Approach 2:
The patent creates a parallel copy of the conversion status information through the pipelined registers, which can be read by the interrupt controller independently of the actual ADC conversion completion. This copying mechanism allows the processor to be notified earlier without requiring the ADC itself to be faster.
3Productivity
If conversion ready delay time is reduced to improve response time, then throughput is improved, but control loop stability may deteriorate
Solution Approach 1:
The patent provides dynamic adjustability of the conversion ready delay time through the selectable pipelined registers. The system can adapt the delay characteristics based on operating conditions, allowing optimization of throughput when stability is less critical and ensuring stability when required, rather than being fixed at a single delay value.
Solution Approach 2:
By changing the selectable delay parameter through different register configurations, the system can optimize performance characteristics. The multiplexer and decoder circuitry enable dynamic parameter selection to match different operational requirements, balancing throughput and stability based on real-time needs.
Data Source
AI summary
An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened.