Physical Parameters Compensation/Prevention TRIZ Cases
- Under-Sampled SAR ADC with Matched Paths for Low Nonlinearity
Matched input and reference paths cancel common distortion in an under-sampled SAR ADC, enabling high bandwidth with lower nonlinearity.
- SAR ADC Capacitor Voltage Coefficient Calibration Using INL
INL-based digital calibration extracts SAR ADC capacitor voltage coefficients to correct nonlinearity without added analog circuitry.
- Magnetometer Readout Circuit for ADC Noise Reduction
A split amplifier and digital correction path cuts ADC noise in magnetometer readout while keeping hardware and power use low.
- Two-Step SAR ADC with Digital Gain Correction for Faster Conversion
Two low-resolution SAR ADCs run concurrently with digital gain correction to raise resolution while improving conversion rate and reducing area.
- NS-SAR ADC Passive Noise Shaping Without Extra Comparator Inputs
Passive residue charge-sharing in an NS-SAR ADC improves SNR without extra comparator input pairs, timing slots, or op-amp power.
- Hybrid Return-to-Zero DAC Driver for Low-Distortion Switching
Alternating return-to-zero sub-drivers cut data-dependent distortion, crowbar currents, and parasitic capacitance in voltage-mode DAC switching.
- Time-Interleaved SAR-ADC Clock Delay Calibration for Skew Control
Variable delay clocks and phase-difference detection correct SAR-ADC skew under IC and environmental fluctuations for accurate conversion.
- Interleaved Switched-Capacitor T/H Calibration for Memory Error Correction
Background calibration corrects memory, kick-back, and order-dependent errors in interleaved switched-capacitor T/H circuits to improve ADC speed and linearity.
- CDR Loop Calibration for Timing Skew in Time-Interleaved ADCs
Shared and per-ADC loop filters separate common and channel phase errors to improve sampling accuracy in time-interleaved ADCs.
- Laser Distance Module Sampling Shift for ADC Error Compensation
Varying ADC sampling instants cancels timing, gain, and offset errors in laser distance modules, improving accuracy and resolution.
- Radiation-Hardened ADC Offset Calibration for TID and SEE
Switched-capacitor sampling and variable-resistor comparator calibration help ADCs resist TID and SEE errors in radiation environments.
- DAC Dummy Stages for Constant Reference Glitch Linearity
Dummy DAC stages keep reference-voltage glitch nearly constant across code changes, sharply reducing harmonic distortion and improving linearity.
- PLL Bandwidth Calibration Using On-Die TDC Closed-Loop Control
On-die TDC and digital loop filter control calibrate PLL bandwidth at reset, avoiding costly off-chip testing and PVT-sensitive analog methods.
- Current DAC Cell Segmentation for Area-Efficient Trimming
Unit cells and larger half cells shrink thermometer-coded DAC layout area while preserving LSB resolution, trimming accuracy, and current control.
- Asynchronous SAR ADC PVT Timing Control for Accurate Fast Conversion
A PVT processor tunes self-timed clock delay and supply voltage so SAR ADCs keep DAC settling accuracy while sustaining fast conversion.
- Bidirectional Oscillator TDC for Phase Noise and Power Noise Cancellation
Using opposite oscillation directions, this TDC cancels phase and power noise so it can share a power supply with less coupling.
- Time-Interleaved DAC Equalization for Sub-DAC Frequency Misalignment
Spur-based calibration equalizes sub-DAC frequency mismatches in time-interleaved DACs using simple spectrum analysis to improve SFDR and ENOB.
- Reservoir Capacitor ADC Reference Buffer Relief for Bit-Trials
Precharged reservoir capacitors supply most bit-trial charge, cutting ADC reference buffer resettling, power use, and conversion errors.
- SAR ADC Switch-Capacitor Calibration for Mismatch Compensation
Lookup-table charge compensation uses switch capacitor groups and a comparator to correct SAR ADC capacitance mismatch without extra calibration circuits.
- Dual-Channel ADC Error Correction With Cyclic Correlation Updates
Cyclic correlation and gradient descent correct clock phase and gain errors in dual-channel ADCs using fewer sample points and faster convergence.
- Laser Distance Module Sampling-Time Shift for ADC Error Compensation
Varying sampling times lets multiple ADC stages capture matching points, averaging out timing, gain, and offset errors in laser distance measurement.