PLL Bandwidth Calibration Using On-Die TDC Closed-Loop Control
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Solution Overview
Problem
Conventional off-chip bandwidth testing for Phase Locked Loops (PLLs) is costly and prone to errors due to process, voltage, and temperature variations, especially in high-volume manufacturing, and existing calibration methods are inefficient and yield-constrained.
Innovation Solution
An on-die apparatus and method for PLL bandwidth calibration using a Time-to-Digital Converter (TDC) and Digital Loop Filter (DLF), which monitors and adjusts digital signals to calibrate PLL bandwidth within a closed loop, allowing for fast, accurate calibration at every PLL reset, using two modulation frequencies to target specific bandwidth ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional off-chip bandwidth testing is used, then measurement capability is provided, but cost increases and manufacturing efficiency decreases
Solution Approach 1:
The patent extracts the bandwidth calibration function from external off-chip testing equipment and implements it directly on the chip using integrated TDC and DLF circuits. This eliminates the need for expensive external signal generators and measurement equipment, thereby reducing cost while maintaining measurement capability and improving manufacturing efficiency through on-chip self-calibration
Solution Approach 2:
The patent implements self-service calibration where the PLL system calibrates its own bandwidth using internal TDC and DLF resources. The system performs self-diagnosis and self-adjustment by monitoring its own phase detector output and adjusting loop filter coefficients accordingly, eliminating dependency on external testing infrastructure and enabling high-volume manufacturing without costly off-chip equipment
2Measurement precision
If conventional off-chip bandwidth testing is used, then measurement capability is provided, but manufacturing cost increases
Solution Approach 1:
The patent extracts the bandwidth calibration function from external off-chip testing equipment and implements it directly on the chip using integrated TDC and DLF circuits. This eliminates the need for expensive external signal generators and measurement equipment, thereby reducing cost while maintaining measurement capability
Solution Approach 2:
The patent creates a digital model/copy of the phase detector output through the TDC, which can be processed and analyzed without requiring physical signal generation and measurement equipment. This digital copying approach enables bandwidth calibration using standard digital processing resources rather than expensive analog testing equipment
3Adaptability or versatility
If analog calibration components are used, then calibration capability is provided, but vulnerability to variations increases
Solution Approach 1:
The patent replaces analog calibration components and continuous analog adjustment mechanisms with digital TDC and DLF circuits that use discrete digital code adjustments. This substitution of digital for analog systems eliminates the vulnerabilities associated with analog component variations, providing robust calibration capability that is insensitive to PVT variations while maintaining adaptability through programmable digital control
4Speed
If fast calibration at every reset is implemented, then calibration speed improves, but system complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-programming the TDC and DLF with calibration algorithms and coefficient sets that enable rapid calibration upon reset. The system prepares calibration data structures and control logic in advance, allowing fast execution during each reset without requiring complex real-time computation, thus achieving fast calibration while managing system complexity through pre-computed solutions
Data Source
AI summary
Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.