Interleaved Switched-Capacitor T/H Calibration for Memory Error Correction
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) face challenges in designing fast, low-power, and accurate track-and-hold circuits due to issues like memory, kick-back, and order-dependent errors, particularly in interleaved switched-capacitor circuits, which affect noise performance, linearity, and frequency response.
Innovation Solution
The proposed solution involves background calibration techniques that account for errors in both track/sample and hold-phases, using dither injection and randomization to correct for memory, kick-back, and order-dependent effects, while simplifying analog circuitry and clocking, and improving noise performance and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If interleaved switched-capacitor track-and-hold circuits are used to increase ADC speed, then conversion speed is improved, but memory errors, kick-back errors, and order-dependent errors increase
Solution Approach 1:
The patent implements background calibration techniques that continuously measure and correct errors in interleaved track-and-hold circuits. Digital correction codes are generated based on measured errors from memory, kick-back, and order-dependent effects, then applied to compensate for these inaccuracies in real-time operation
Solution Approach 2:
The patent modifies circuit parameters through calibration by adjusting digital correction codes that compensate for errors. The system changes the effective transfer characteristics of the track-and-hold circuits by applying correction values that counteract the harmful effects of interleaving, thereby maintaining signal accuracy at high conversion speeds
2Reliability
If complex calibration techniques are applied to correct errors in track-and-hold circuits, then signal accuracy is improved, but circuit complexity and power consumption increase
Solution Approach 1:
The patent implements self-calibrating circuitry that automatically measures and corrects its own errors without external intervention. The calibration system uses the circuit's own output signals to generate correction codes, eliminating the need for external calibration equipment or complex manual adjustment mechanisms
Solution Approach 2:
The patent replaces complex analog calibration circuitry with digital correction techniques. Instead of using intricate analog components to correct errors, the system uses digital signal processing and correction codes applied in the digital domain, simplifying the analog circuitry while maintaining correction effectiveness
3Manufacturing precision
If dither injection and randomization are used to correct errors, then linearity and noise performance are improved, but circuit complexity increases
Solution Approach 1:
The patent employs periodic dither injection where a small random signal is added to the input signal at controlled intervals. This periodic dithering action helps linearize the transfer characteristic of the track-and-hold circuits by preventing the system from operating in non-linear regions, thereby improving linearity without requiring continuous complex circuitry
Solution Approach 2:
The patent introduces dither signals as an intermediary element that mediates between the input signal and the non-linear track-and-hold circuitry. The dither signal acts as a buffer that prevents direct interaction between the input signal and the non-linearities of the switching circuitry, thereby improving linearity and noise performance
Data Source
AI summary
Background calibration techniques can effectively to correct for memory, kick-back, and order-dependent errors in interleaved switched-capacitor track-and-hold (T/H) circuits and amplifiers. The techniques calibrate for errors in both the track/sample phase and the hold-phase, and account for the effects of interleaving, buffer/amplifier sharing, incomplete resetting, incomplete settling, chopping, and randomization on the offset, gain, memory, and kick-back errors. Moreover, the techniques can account for order-dependent and state-dependent hold-phase non-linearities. By correcting for these errors, the proposed techniques improve the noise performance, linearity, gain/offset matching, frequency response (and bandwidth), and order-dependence errors. The techniques also help increase the speed (sample rate and bandwidth) and linearity of T/H circuits and amplifiers while simplifying the analog circuitry and clocking needed. These techniques comprehensively account for various memory, kick-back, and order-dependent effects in a unified framework.