Current DAC Cell Segmentation for Area-Efficient Trimming
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Solution Overview
Problem
Thermometer coded digital-to-analog converters (DACs) typically consume a large area in chip floor plans due to their array configuration, leading to accuracy degradation and inefficiencies in current trimming and selection processes.
Innovation Solution
The design incorporates a current DAC with unit cells and half cells, where half cells have twice the size but handle half the current, allowing for a more area-efficient layout by using a combination of unit cells and half cells in offset and trimming arrays, which can be selectively activated to maintain accuracy and control current output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional thermometer coded DAC uses only unit cells in array configuration, then the current trimming and selection can be performed, but the chip area consumption is large leading to accuracy degradation
Solution Approach 1:
The DAC array is segmented into two distinct types of cells: unit cells and half cells. Unit cells contain a single current generation transistor, while half cells contain two current generation transistors connected in series. This segmentation allows the DAC to achieve the same current resolution with fewer total cells, reducing chip area while maintaining accuracy.
Solution Approach 2:
Different regions of the DAC array use different cell types optimized for different purposes. Half cells are used where smaller current steps are needed (providing finer resolution), while unit cells are used where larger current steps are acceptable. This local optimization allows the overall array to achieve high accuracy with reduced area consumption.
2Area of stationary object
If half cells with larger size are used to handle half current amount, then the layout area is reduced, but the cell structure complexity increases
Solution Approach 1:
The cell structure is segmented into standardized components (current generation transistors, row select transistor, column select transistor) that can be systematically combined. Half cells simply add one more transistor in series, following the same modular pattern as unit cells, which keeps the overall system manageable despite increased complexity.
Solution Approach 2:
Both unit cells and half cells use the same select transistor structure (row select and column select transistors), making the selection mechanism universal across different cell types. This universality simplifies the control logic and reduces the overall system complexity despite the diversity in cell structures.
Data Source
AI summary
A current digital to analog converter (DAC) including an offset array including a plurality of unit cells of a first size, and a trimming array including a plurality of unit cells having the first size and a plurality of half cells, wherein the half cells have a larger size than the plurality of unit cells.