Two-Step SAR ADC with Digital Gain Correction for Faster Conversion
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Solution Overview
Problem
High resolution SAR ADCs are limited by the serial decision-making process and require significant time for voltage settling due to large sampling capacitors, which restricts their conversion rate.
Innovation Solution
A novel two-step SAR ADC method couples two low-resolution SAR ADCs with an amplifier, allowing them to perform a binary search process concurrently, aligning and summing their outputs to achieve higher resolution and faster conversion rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high resolution SAR ADC is implemented, then resolution is improved, but conversion rate deteriorates due to large sampling capacitor requiring significant settling time
Solution Approach 1:
The patent divides a high-resolution ADC conversion into two sequential steps: first converting the most significant bits (MSBs) and then converting the least significant bits (LSBs). This segmentation allows each conversion step to use smaller capacitors, reducing settling time while maintaining overall high resolution. The first SAR ADC converts MSBs with a coarse capacitor array, and the second SAR ADC converts LSBs with a fine capacitor array, enabling faster conversions without sacrificing resolution.
Solution Approach 2:
The patent implements a nested structure where the output of the first SAR ADC (MSB conversion) serves as an input reference for the second SAR ADC (LSB conversion). The residue voltage from the first conversion is fed into the second conversion stage, creating a nested two-step conversion process. This nesting allows the system to achieve high resolution by combining results from two lower-resolution conversions.
2Measurement precision
If high resolution SAR ADC is implemented, then resolution is improved, but time consumption worsens due to serial decision making process
Solution Approach 1:
The patent segments the serial decision-making process into two parallel SAR ADC operations. Instead of one long serial conversion, the system performs two shorter serial conversions in sequence, where the first converts MSBs and the second converts LSBs. Each segment requires fewer comparison steps, reducing total conversion time while maintaining high resolution through the combination of both results.
Solution Approach 2:
The patent performs preliminary conversion of the most significant bits first, establishing a coarse approximation before refining with the least significant bits. This preliminary action allows the system to quickly establish the major portion of the conversion result, reducing the time required for the overall high-resolution conversion compared to performing all bits in a single serial process.
3Measurement precision
If high resolution SAR ADC is implemented, then resolution is improved, but silicon area worsens due to large capacitor requirements
Solution Approach 1:
The patent segments the capacitor array into two separate, smaller capacitor arrays used in sequence, rather than requiring one large capacitor array for high-resolution conversion. The first SAR ADC uses a coarse capacitor array for MSB conversion, and the second SAR ADC uses a fine capacitor array for LSB conversion. This segmentation dramatically reduces the total silicon area required, as the sum of two small capacitor arrays is much less than one large capacitor array of equivalent total resolution.
Solution Approach 2:
The patent employs a nested capacitor structure where the residue voltage from the first conversion stage is processed by the second conversion stage with its own smaller capacitor array. This nesting allows the system to achieve high resolution without requiring a single large capacitor array, as each nested stage uses only the capacitor size necessary for its specific resolution requirement.
Data Source
AI summary
A new SARADC has two low resolution SAR (Successive Approximation Register) ADCs coupled together by an amplifier to increase the overall resolution and enhance ADC conversion rate. The gain reduction of amplifier is corrected by shifting the digital binary output position. Two SAR ADC outputs are timing aligned and summed to produce final high-resolution high conversion rate ADC output.