Under-Sampled SAR ADC with Matched Paths for Low Nonlinearity
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Solution Overview
Problem
Under-sampled successive approximation register (SAR) analog to digital converters (ADCs) face challenges in achieving high bandwidth while minimizing nonlinearity issues, particularly due to the pedestal effect and distortion, which require complex compensation circuits and calibration schemes, increasing design complexity and power consumption.
Innovation Solution
The implementation of a high bandwidth under-sampled SAR ADC with matched signal paths for the input and reference signals, using a dual clock structure with a controllable phase offset and an asymmetrical driver to minimize drift and nonlinearity, allowing for resampling at each step and canceling out common distortion effects through signal subtraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex compensation circuits and calibration schemes are used to address non-linearity and distortion, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent converts the harmful pedestal effect and distortion into a beneficial common-mode signal that can be rejected. By intentionally allowing both the input signal path and reference signal path to experience the same non-linearities and distortions, these effects become common to both paths and can be eliminated through differential processing, thereby improving linearity without adding complex compensation circuits
Solution Approach 2:
The matched signal paths serve multiple functions: they provide the necessary signal routing for conversion, intentionally introduce identical non-linearities to both paths, and enable common-mode rejection. This multi-functionality eliminates the need for separate compensation circuits, reducing overall device complexity while maintaining high measurement precision
2Measurement precision
If complex compensation circuits are implemented to mitigate distortion, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent eliminates the need for energy-consuming compensation circuits by converting harmful non-linearities into beneficial common-mode signals. The matched signal paths intentionally experience the same distortions, which are then rejected through differential processing, achieving high linearity performance without the power overhead of active compensation mechanisms
Solution Approach 2:
The system uses itself to cancel out its own non-linearities. By ensuring both the input and reference paths experience identical distortions, the ADC automatically generates the necessary cancellation signal through its own operation, eliminating the need for external compensation circuits and reducing power consumption
3Speed
If sampling rate is increased to achieve high bandwidth operation, then speed is improved, but nonlinearity and distortion increase
Solution Approach 1:
The patent converts the high-speed sampling-induced distortions into beneficial common-mode signals. By ensuring both signal paths experience the same speed-related non-linearities, these distortions become rejectable through differential processing, enabling high bandwidth operation without sacrificing linearity performance
Data Source
AI summary
Described herein are apparatus and methods for a high bandwidth under-sampled successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with non-linearity minimization. A method includes sampling, by a sampling switch triggered by a sampling clock in the SAR ADC, an input signal, determining, by a comparator in the SAR ADC, a value for a bit based on comparing the sampled input signal to a reference signal provided by a reference digital-to-analog (DAC) in the SAR ADC, wherein the input signal and the reference signal propagate through substantially similar input paths, resampling, by the sampling switch, the input signal for each successive bit, determining, by the comparator, a value for each successive bit based on comparing the resampled input signal and a reference signal for each successive bit, and outputting, by a digital controller, a digital result after determining a value for a last bit by the comparator.