Parallel ADC Sub-Channel Compensation for Gain Offset and Skew

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Solution Overview

Problem

Existing data communication systems face challenges in achieving high data processing and exchange rates due to limitations in analog-to-digital converter (ADC) speed and performance, leading to issues like DC offset, gain offset, and skew when distributing high data rate signals into multiple sub-channels for processing.

Innovation Solution

A method and apparatus utilizing a time-interleaving analog-to-digital conversion system with multiple ADCs, each operating at a lower clock rate, and incorporating DC offset compensation, sub-channel gain mismatch compensation, and de-skew systems to ensure accurate signal processing and recombination across sub-channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the A/D converter operates at higher rates to accommodate increased data exchange rates, then the data processing speed is improved, but the performance deteriorates due to ADC speed limitations and inability to maintain desired performance levels

Engineering Contradiction:
Improvedata processing speedVSAvoidconversion performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides a single high-speed A/D conversion task into multiple parallel lower-speed conversions. The analog signal is split into multiple sub-channels, each processed by separate A/D converters operating at reduced clock rates. This segmentation allows the system to achieve high overall data rates while each individual converter maintains reliable performance within its speed capabilities.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the high data rate signal is split into multiple sub-channels for distributed processing, then the processing rate for each signal is reduced, but signal mismatches occur due to processing variations across sub-channels

Engineering Contradiction:
Improveprocessing rate per signalVSAvoidsignal consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements feedback mechanisms that monitor and measure processing variations across sub-channels. By continuously detecting differences in gain, DC offset, and skew between sub-channels, the system can generate correction signals that are fed back to compensate for these variations, thereby maintaining signal consistency across all parallel paths.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent dynamically adjusts processing parameters for each sub-channel to compensate for variations. By changing gain levels, DC offsets, and timing parameters based on detected differences, the system equalizes the processing characteristics across all sub-channels, ensuring consistent signal quality despite manufacturing tolerances and clock variations.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If multiple sub-channels are used for parallel processing, then the overall data exchange rate is increased, but DC offset, gain offset, and skew variations occur between sub-channels

Engineering Contradiction:
Improvedata exchange rateVSAvoidsignal parameter accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent employs feedback loops that continuously monitor DC offset, gain, and skew parameters across sub-channels. Correction signals are generated based on these measurements and applied to each sub-channel to eliminate parameter variations, ensuring accurate signal representation despite the use of multiple parallel paths.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces intermediary correction circuits between the sub-channels and the final signal combination point. These intermediary elements (such as gain control circuits, DC offset compensation circuits, and timing adjustment circuits) act as mediators that equalize the signal parameters before recombination, preventing parameter variations from affecting the overall output accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP2015454B1Sub-channel distortion mitigation in parallel digital systems
Publication Date: 2013.08.07 MARVELL INT LTD
  • EP2015454B1 patent drawingFigure 1
  • EP2015454B1 patent drawingFigure 2
  • EP2015454B1 patent drawingFigure 3~4

AI summary

A method and apparatus for compensating for gain offset, bias offset, and skew in a parallel processing environment is disclosed. The method and apparatus may be configured to compensate for mismatches between the sub-channel signals in a parallel ADC. This allows for accurate combination of the signals on the sub-channels. The method and apparatus may be utilized in a high speed data communication system having two or more channels, each of which are interleaved into two or more sub-channels. In one embodiment a DC loop processes signals on two or more sub-channels to account for and remove unwanted bias offset. In one embodiment a sub-channel gain mismatch compensation system (SCGMC) processes signals on two or more sub-channels to account for and remove unwanted gain offset. In one embodiment a skew compensation system, such as a parallel interpolator, processes signals on two or more sub-channels to remove unwanted skew across sub-channels.