PLL Bandwidth Calibration with On-Die TDC Closed-Loop Control
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Solution Overview
Problem
Conventional off-chip bandwidth testing for Phase Locked Loops (PLLs) is costly and prone to errors due to process, voltage, and temperature variations, especially in high-volume manufacturing, and existing calibration methods are inefficient and yield-constrained.
Innovation Solution
An on-die apparatus and method for PLL bandwidth calibration using a Time-to-Digital Converter (TDC) and Digital Loop Filter (DLF), which monitors and adjusts digital signals to calibrate PLL bandwidth within a closed loop, employing modulation frequencies and adjustable filter coefficients for precise calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional off-chip bandwidth testing is used, then measurement capability is provided, but cost becomes prohibitive for high volume manufacturing
Solution Approach 1:
The patent extracts the bandwidth calibration function from external off-chip test equipment and implements it directly on the chip using integrated TDC and DLF circuits. This eliminates the need for expensive external signal generators and test equipment, making the solution cost-effective for high volume manufacturing while maintaining measurement capability
Solution Approach 2:
The PLL system performs its own bandwidth calibration using on-chip resources. The TDC measures phase differences and the DLF filters signals to determine optimal bandwidth settings, enabling the system to self-calibrate without external intervention. This self-service approach eliminates costly external testing while maintaining measurement precision
2Ease of operation
If analog calibration components are used, then calibration interface is provided, but vulnerability to variation increases
Solution Approach 1:
The patent replaces analog calibration components and interfaces with fully digital circuits. The TDC converts phase differences to digital values, and the DLF processes digital signals to determine bandwidth settings. This digital implementation eliminates vulnerability to analog variations while maintaining calibration functionality
Solution Approach 2:
The patent changes the calibration interface from analog voltage/frequency signals to digital parameters. The TDC outputs digital phase difference values, and the system adjusts digital control words to the VCO based on DLF analysis. This parameter transformation from analog to digital domain eliminates sensitivity to analog variations
3Ease of manufacture
If analog PLL components are used, then PLL functionality is provided, but process variation impact increases
Solution Approach 1:
The patent replaces analog PLL components with digital implementations where possible. The TDC uses digital delay elements and counters, the DLF uses digital filtering, and the control interface is digital. This digital substitution reduces sensitivity to process variations while maintaining PLL functionality
Solution Approach 2:
The patent implements a feedback mechanism where the TDC continuously measures phase differences between reference and feedback clocks, the DLF analyzes these measurements to determine bandwidth settings, and the system adjusts VCO control accordingly. This closed-loop feedback compensates for process variations and maintains consistent PLL bandwidth across manufacturing batches
Data Source
AI summary
Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.