CDR Loop Calibration for Timing Skew in Time-Interleaved ADCs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges in maintaining equal phase differences between samples due to timing/phase skew or mismatch, which affects the accuracy of signal sampling, especially in high-speed communication systems.
Innovation Solution
A time-interleaved analog-to-digital convertor system that includes an array of ADCs, a clock and data recovery (CDR) circuit with first-order loop filters for ADC-specific corrections and a shared loop filter for collective phase error correction, utilizing a voltage-controlled oscillator (VCO) and phase generator circuitry to provide corrected phase-shifted clock signals, and employing algorithms like early-late or Mueller-Muller for phase error computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved ADCs are used to accommodate very high sampling rates, then the sampling rate is improved, but timing/phase skew between adjacent samples occurs
Solution Approach 1:
The patent divides the phase error correction into two independent segments: a shared loop filter that processes the sum of phase errors from all ADCs to correct common timing skew, and individual loop filters that process each ADC's specific phase errors. This segmentation allows the system to maintain high sampling rates while correcting both common and individual timing/phase skew, thereby resolving the contradiction between speed and measurement precision.
2Measurement precision
If multiple loop filters are used for both shared and individual phase error corrections, then the phase error correction is improved, but the device complexity increases
Solution Approach 1:
The correction system is segmented into a shared loop filter handling common phase errors and individual loop filters handling ADC-specific phase errors. This segmentation improves correction accuracy by addressing different error sources separately while keeping each filter's design relatively simple and modular.
Solution Approach 2:
The patent merges the correction of common phase errors (affecting all ADCs) and individual phase errors (affecting specific ADCs) into a unified correction framework. The shared loop filter outputs a common correction applied to all ADCs, while individual loop filters provide additional ADC-specific corrections, achieving high precision without requiring a completely separate correction path for each error source.
3Measurement precision
If individual phase corrections are applied to each ADC, then the individual timing skew is improved, but the shared timing skew correction becomes less effective
Solution Approach 1:
The patent segments the phase error correction into two independent but complementary paths: a shared loop filter that processes the sum of all phase errors to correct common timing skew affecting all ADCs, and individual loop filters that process each ADC's specific phase errors. This segmentation ensures that both shared and individual timing skews are corrected effectively, resolving the contradiction between individual timing accuracy and shared timing synchronization.
Solution Approach 2:
The system employs feedback mechanisms where the output of each ADC is fed back through its respective loop filter, and the sum of all outputs is fed back through the shared loop filter. This feedback allows the system to continuously monitor and correct both individual and shared phase errors, maintaining reliable timing synchronization while achieving high individual timing accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively corrects both shared and individual phase errors, improving sampling accuracy and reducing noise effects, thereby enhancing the performance of time-interleaved ADCs in high-speed communication systems.
Implementation Method 1
utilizing a voltage-controlled oscillator (VCO) and phase generator circuitry to provide corrected phase-shifted clock signals
Data Source
AI summary
In one embodiment, a time-interleaved analog-to-digital convertor (ADC) system, includes an array of ADCs to sample respective analog voltages at sampling times indicated by respective clock signals and to output corresponding digital values, phase generator circuitry to provide multiple, different phase-shifted clock signals for driving the respective sampling times of the ADCs, and a clock and data recovery circuit including ADC-specific first-order loop filters to derive respective ADC-specific average phase error corrections, and a shared loop filter to derive a shared average phase error correction over the array of ADCs and wherein the phase generator circuitry is coupled to provide corrected respective ones of the phase-shifted clock signals responsively to both respective ones of the ADC-specific average phase error corrections derived by respective ones of the first-order loop filters, and the shared average phase error correction derived by the shared loop filter.