ADC Fault Detection Using Window Triggered Redundant Sampling
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Solution Overview
Problem
Existing systems face challenges in ensuring the integrity and reliability of analog input signals, particularly in industrial automation, where redundant circuits or external monitors are costly and power-intensive, making it difficult to detect and respond to abnormal signals effectively.
Innovation Solution
An ADC circuit that operates in on-demand or input-driven modes, using a programmable clock circuit and comparison circuitry to automatically reconfigure and perform redundant comparisons, setting a safety fault flag if errors exceed a predetermined tolerance, thereby reducing the need for redundant monitor circuits and maintaining digital output usage during error checking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant circuits or external monitors are used to ensure signal integrity, then reliability is improved, but power consumption and cost increase
Solution Approach 1:
The patent combines the ADC's normal conversion function with fault detection capability into a single integrated circuit. The same ADC core is used for both analog-to-digital conversion and for generating redundant conversion results through reconfiguration, eliminating the need for separate redundant circuits or external monitor devices. This merging approach maintains reliability while reducing power consumption and cost.
Solution Approach 2:
The ADC circuit is designed to perform multiple functions: normal analog-to-digital conversion and fault detection. By reconfiguring the same hardware resources (ADC cores, multiplexers, clock circuits) to generate and compare redundant conversion results, the system achieves monitoring capability without adding dedicated redundant components, thereby reducing power consumption and cost while maintaining signal integrity.
2Reliability
If redundant circuits or external monitors are used to detect abnormal signals, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges fault detection functionality into the existing ADC structure by reconfiguring available components. The same ADC cores, multiplexers, and clock circuits are used for both normal operation and fault detection, avoiding the addition of separate redundant circuits or external monitor devices. This integration maintains reliability while minimizing increases in device complexity.
3Measurement precision
If the ADC performs redundant comparisons to ensure signal integrity, then measurement precision is improved, but productivity decreases
Solution Approach 1:
The patent implements fault detection as a periodic or on-demand operation rather than continuous processing. The ADC reconfigures to perform redundant conversions only when fault detection is needed (input-driven mode) or at scheduled intervals (on-demand mode), allowing normal high-speed conversion to continue otherwise. This periodic approach maintains measurement precision through verification while minimizing impact on overall productivity.
Solution Approach 2:
The system dynamically reconfigures the ADC operation mode based on requirements. The programmable clock circuit and multiplexers allow the ADC to switch between normal conversion mode (high productivity) and fault detection mode (high precision verification). This dynamic adaptation enables the system to optimize between measurement precision and productivity based on real-time needs.
Data Source
AI summary
A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC.