Physical Parameters Compensation/Prevention TRIZ Cases

A time-to-digital converter measures per-cell DAC skew so timing errors can be corrected, improving linearity and noise without larger devices.

Correlation-based dither extraction and adaptive correction improve ADC linearity and signal-to-noise ratio despite process variation.

Logic flags conversions as noisy during overlapping ADC activity, preserving deterministic sample rates on a single die.

Clamping a high-impedance SAR ADC node near a diode drop stabilizes decisions and improves conversion accuracy and efficiency.

Correction-code feedback regulates differential input common-mode voltage in a SAR ADC to shorten comparator decision time and sustain high-speed conversion.

Independent analog reconstruction compares DAC output with the original input to detect digital control development errors and improve reliability.

Randomized thermometric encoding spreads DAC mismatch across codes, shifting spurious tones away from the band of interest to preserve dynamic range.

A dead-band switch isolates the DAC bias node during data transitions to cut inter-cell interference, odd-order harmonics, and distortion.

Controller-based gain calibration and offset cancellation improve residue amplification accuracy in pipeline SAR ADC inter-stage transfer.

NRZ-based calibration and genetic-parameter correction reduce TI-ADC mismatch overhead while improving accuracy across wide frequencies.

Logic marks ADC results as noisy during overlapping sample-convert periods, enabling single-die multi-ADC operation with stable sample rates.

Feedback-based calibration uses echo signals and offset tables to cancel mismatch echoes and improve DAC conversion accuracy.

Capacitive voltage division at the comparator gate suppresses inversion timing error, reducing ADC nonlinearity, noise, and image degradation.

A switching sample-and-hold path and resistor-ladder DAC cut capacitor use in sigma-delta ADCs, reducing size, power, and delay.

Temperature-dependent bulk biasing offsets MOS body effect in W-2W current mirrors, preserving SET pulse shape and linearity in phase-change memory.

Window-triggered ADC reconfiguration boosts clock rate and alternates inputs for redundant comparison without separate monitor circuits.

Redundant MSB approximation and LSB-based detection let a SAR ADC identify faulty comparators and correct offset-driven conversion errors.

Distributed frequency multiplication inside DAC cells generates higher-frequency analog output while lowering LO clock power and architecture complexity.

A negative pre-charge at the comparator input steepens the DTC ramp without shortening ramp time, cutting random jitter in FOD timing.

Digital pre-compensation corrects DAC rise/fall asymmetry, amplitude mismatch, and timing offset to improve SNDR with lower complexity and power.

Parallel ADC circuits use phase-shifted cyclic sampling, bit prediction, and residue noise shaping to raise conversion speed without sacrificing SNR.

A low-pass filter and stored capacitor offset let pipelined ADC residue amplifiers cancel drift in real time and stay within redundancy range.

Optimized non-binary current-source weights cut glitch, static, and timing offset errors in DACs while avoiding segmented-switch complexity.

A virtual ADC extracts valid DAC output samples to calibrate offset, gain, and timing without costly high-speed transmit-side ADCs.

A segmented comparator supply holds pMOS drain voltage steady at signal crossover, reducing inversion timing errors and ADC non-linearity.

Channel-specific reference voltages and calibration feedback correct interleaved ADC full-scale mismatch without noise-amplifying post-processing.

Alternating low- and high-precision comparators with uneven redundancy allocation speeds SAR ADC conversion while preserving accuracy and lowering calibration overhead.

A feedforward noise-shaping loop boosts ADC resolution in short conversion times while lowering power and supporting multiplexed channels.

Multiple ADCs sampled at different rates isolate shared bandwidth, letting common-mode filtering suppress spurs and improve dynamic range.

A shared ADC and multiplexer scheme preserves redundant thermal sensing for ASIL-D while cutting ADC count, die area, and circuit complexity.

Variable current sources and phase interpolation cut SerDes clock jitter while extending phase delay range at low power.

A complex polynomial correction function in FPGA logic suppresses conversion-circuit intermodulation in oversampled narrowband signals.

On-demand ADC self-checking compares channel conversions and raises fault flags without external monitors, cutting power and cost.

Pseudo-periodic estimation and clock-phase randomization help time-interleaved ADCs correct DC offset and mismatch spurs below the noise floor.

Digital gain-error extraction and coding reconstruction improve pipelined ADC accuracy while relaxing op-amp gain and bandwidth demands.

Internal test-signal switching lets interleaved ADC channels self-calibrate and correct interleave errors without external equipment.

ADC sampling is tuned so harmonic aliasing stays away from base frequencies, enabling parallel touch scans with higher frame rates and better accuracy.

A feedback calibration loop estimates interchannel clock skew and corrects phase convergence errors to preserve ADC resolution and linearity.

A two-phase digital-slope quantizer boosts ADC speed and resolution while reducing comparator offset sensitivity, calibration burden, and power use.

Matched input and reference paths cancel common distortion in an under-sampled SAR ADC, improving bandwidth and linearity with less power.

Pseudo-random sampling clock phase adjustment in a TIADC suppresses residual skew tones and improves SFDR.

Separate full-scale reference paths calibrate interleaved ADC gain mismatch from PVT variation while avoiding noise amplification.

A gradient-agnostic switching sequence cuts process-gradient output variation in configurable circuits without changing layout or process.

Bit-distribution monitoring corrects comparator offset mismatch in SAR ADCs, improving linearity without dedicated offset correction cycles.

Split bleeder source switching cuts RF DAC mismatch spurs and HD2 leakage while keeping noise spectral density low.

Larger ADC clock phase shifts are paired with updated echo-canceller tap coefficients to cut phase selector cost without hurting signal quality.

A two-stage ADC uses digital slope conversion and residual noise shaping to improve low-frequency SNR without the power cost of full high-performance ADCs.

Three resistor-derived reference levels let a single-slope ADC cancel comparator delay and offset without precise resistor matching.

Transparent dither and observer ADC cross-correlation measure RF DAC timing skew in background, improving high-frequency output quality.

A parallel coarse ADC guides VTDC residue generation to remove common-mode delay, improving conversion speed, resolution, and power use.