SAR ADC Comparator Error Detection With Redundant MSB Approximation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Successive-approximation register analog-to-digital converters (SAR ADCs) face challenges in accurately detecting comparator errors, which affect the accuracy of their output, as existing methods lack effective mechanisms for error detection and compensation.
Innovation Solution
A SAR ADC with a comparator error detector is designed, incorporating a digital-to-analog converter, multiple comparators, and successive-approximation logic, which includes redundancy approximation and a comparator error detector that identifies and corrects errors by determining the target comparator causing the error based on most significant and least significant bits, thereby improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SAR ADC design is used, then the device complexity is low, but the measurement precision and reliability are insufficient due to inability to detect comparator errors
Solution Approach 1:
The patent divides the comparator error detection function into separate modules: an error detection unit that monitors comparator outputs, an error identification unit that locates the specific faulty comparator, and a compensation unit that corrects the error. This segmentation allows the system to detect and correct comparator errors without requiring a complete redesign of the entire SAR ADC structure, thus improving measurement precision while controlling device complexity.
Solution Approach 2:
The patent introduces an intermediary error detection and compensation mechanism that acts between the comparators and the SAR logic. This intermediary layer monitors comparator outputs, identifies errors through analysis of least significant bits, and applies compensation without disrupting the core SAR conversion process, thereby improving reliability while maintaining relatively simple device architecture.
2Reliability
If redundancy approximation is added to the lowest bit of most significant bits, then the ability to detect and correct errors is improved, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by introducing redundancy approximation at the lowest bit of the most significant bits before the actual conversion process. This redundancy is pre-configured in the digital-to-analog converter, allowing the system to detect and correct comparator errors during the conversion process without requiring additional complex error correction mechanisms to be added dynamically.
Solution Approach 2:
The patent utilizes parameter changes by modifying the digital control bits at the redundant bit position to detect comparator errors. By monitoring changes in the least significant bits and analyzing patterns in the digital control bits, the system can identify which comparator is faulty and apply appropriate compensation, improving reliability through parameter monitoring without adding substantial structural complexity.
3Measurement precision
If multiple MSB comparators are used corresponding to most significant bits, then the measurement precision is improved, but the difficulty of detecting and measuring comparator errors increases
Solution Approach 1:
The patent implements feedback by using the least significant bits as feedback signals to monitor the operation of MSB comparators. The error detection unit continuously analyzes the LSB outputs and uses this feedback information to identify which MSB comparator is producing errors. This feedback mechanism enables automatic error detection and identification without requiring complex external testing equipment or disrupting the normal conversion process.
Solution Approach 2:
The patent applies self-service by enabling the SAR ADC system to automatically detect and identify comparator errors using its own internal signals. The error detection unit utilizes the existing least significant bits and digital control bits already present in the system to identify faulty comparators, without requiring external intervention or additional complex diagnostic circuits, thus reducing the difficulty of error detection while maintaining high measurement precision.
Data Source
AI summary
A successive-approximation register analog-to-digital converter (SAR ADC) with comparator error detection is shown, which introduces a comparator error detector to detect errors of the comparators used in the SAR ADC. Digital control bits controlling a digital-to-analog converter (DAC) of the SAR ADC include most significant bits (MSBs) and least significant bits (LSBs), and the DAC is configured to provide redundancy approximation at the lowest bit of the MSBs. The comparators include a plurality of MSB comparators corresponding to the MSBs. The comparator error detector detects the occurrence of a comparator error based on the LSBs, and identifies the target comparator that is causing the comparator error based on the MSBs.