Continuous-Time Sigma-Delta ADC With Switching Quantizer Path
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Solution Overview
Problem
Existing sigma-delta analog-to-digital converters (ADCs) face challenges in reducing size and power consumption due to the use of capacitor-based sample-and-hold circuits and capacitive digital-to-analog converters (DACs), which also increase delay and cost.
Innovation Solution
The proposed solution is a continuous-time sigma-delta ADC that replaces capacitor-based circuits with a switching architecture for sample-and-hold functionality and a resistor-ladder DAC, reducing the need for capacitors and thereby minimizing size, power consumption, and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitor-based sample-and-hold circuits and capacitive DACs are used in sigma-delta ADCs, then the ADC can achieve proper signal sampling and conversion, but the size, power consumption, and delay increase
Solution Approach 1:
The patent extracts and removes capacitors from the ADC architecture, replacing capacitor-based sample-and-hold circuits with switching circuits and capacitive DACs with resistor-ladder DACs. This extraction eliminates the primary source of large area consumption while maintaining the essential signal sampling and conversion functions through alternative circuit implementations.
Solution Approach 2:
The patent substitutes electrical component types to resolve the contradiction. Specifically, it replaces capacitive elements with resistive elements in the DAC architecture and replaces capacitor-based switching with transistor-based switching circuits. This substitution fundamentally changes the physical basis of the circuit operation from capacitive storage to resistive division and transistor switching, thereby reducing area while maintaining functionality.
2Reliability
If capacitor-based sample-and-hold circuits and capacitive DACs are used in sigma-delta ADCs, then the ADC can achieve proper signal sampling and conversion, but power consumption increases
Solution Approach 1:
The patent extracts and removes capacitors from the ADC architecture, replacing capacitor-based sample-and-hold circuits with switching circuits and capacitive DACs with resistor-ladder DACs. This extraction eliminates the primary source of large area consumption while maintaining the essential signal sampling and conversion functions through alternative circuit implementations.
Solution Approach 2:
The patent substitutes electrical component types to resolve the contradiction. Specifically, it replaces capacitive elements with resistive elements in the DAC architecture and replaces capacitor-based switching with transistor-based switching circuits. This substitution fundamentally changes the physical basis of the circuit operation from capacitive storage to resistive division and transistor switching, thereby reducing area while maintaining functionality.
3Reliability
If capacitor-based sample-and-hold circuits and capacitive DACs are used in sigma-delta ADCs, then the ADC can achieve proper signal sampling and conversion, but delay increases
Solution Approach 1:
The patent extracts and removes capacitors from the ADC architecture, replacing capacitor-based sample-and-hold circuits with switching circuits and capacitive DACs with resistor-ladder DACs. This extraction eliminates the primary source of large area consumption while maintaining the essential signal sampling and conversion functions through alternative circuit implementations.
Solution Approach 2:
The patent substitutes electrical component types to resolve the contradiction. Specifically, it replaces capacitive elements with resistive elements in the DAC architecture and replaces capacitor-based switching with transistor-based switching circuits. This substitution fundamentally changes the physical basis of the circuit operation from capacitive storage to resistive division and transistor switching, thereby reducing area while maintaining functionality.
Data Source
AI summary
In some examples, a circuit includes a first integrator having an input and an output. The circuit also includes a switching architecture having first and second terminals, the first terminal of the switching architecture coupled to the output of the first integrator. The circuit also includes a second integrator having an input and an output, the input of the second integrator coupled to the second terminal of the switching architecture. The circuit also includes a quantizer having an input and an output, the input of the quantizer coupled to the output of the second integrator. The circuit also includes a digital processing circuit having an input and an output, the input of the digital processing circuit coupled to the output of the quantizer.


