Interleaved ADC Full-Scale Reference Calibration for Gain Matching

The patent introduces a separate calibration signal path that acts as an intermediary to measure and characterize mismatch errors without using the main signal path. A calibration signal is injected through dedicated calibration switches and measured by the ADCs, allowing error characterization without amplifying noise in the primary signal path. This mediator approach separates the measurement function from the signal processing function.

The patent replaces digital post-processing correction with an analog calibration approach. Instead of using digital multiplication of adjustable coefficients to correct mismatch errors, the system uses analog calibration signals and open-loop buffers to establish accurate full-scale reference voltages before conversion, substituting digital correction mechanisms with analog reference voltage establishment.

The patent segments the full-scale reference generation into separate independent sources for each ADC channel. Instead of using a single common reference voltage that couples noise among all ADCs, the system provides individual full-scale reference voltages to each ADC through separate buffer circuits. This segmentation isolates noise sources while maintaining reference accuracy for each channel independently.

The patent introduces open-loop buffer circuits as intermediary elements between the reference voltage source and each ADC. These buffers act as mediators that provide accurate full-scale reference voltages to each ADC channel without direct coupling between channels, preventing noise propagation while maintaining reference integrity.

The patent applies preliminary calibration action before the ADCs operate in their normal parallel sampling mode. A calibration phase is performed where mismatch errors are measured using calibration signals, and correction factors are determined. These preliminary measurements allow the system to compensate for gain and offset differences among the N ADCs before they process the actual high-speed signal, enabling accurate parallel operation despite process, voltage, and temperature variations.

The patent implements feedback through the calibration process where mismatch errors are measured and used to adjust correction factors. The calibration system measures the actual response of each ADC using injected calibration signals, determines the deviation from ideal behavior, and applies correction factors to compensate for these deviations. This feedback loop enables the parallel ADC system to maintain measurement precision despite variations in process, voltage, and temperature.