Noise-Shaping Digital Slope ADC for Low-Power High Resolution
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) face a trade-off between performance, noise levels, bandwidth, and power consumption, failing to meet strict requirements for high performance and low power consumption.
Innovation Solution
The proposed ADC device incorporates a digital slope ADC circuitry with a slope generator, delay line, comparator, and noise shaping circuit to generate bits and perform noise shaping functions, optimizing voltage adjustments and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional ADC circuitry is used to achieve high performance, then resolution and bandwidth are improved, but power consumption increases
Solution Approach 1:
The ADC is divided into two independent circuitries: a first ADC circuitry that performs initial conversion and generates first bits, and a second digital slope ADC circuitry that performs subsequent conversion and generates second bits. This segmentation allows each circuit to be optimized for its specific function, with the digital slope ADC consuming less power for the remaining conversion steps.
Solution Approach 2:
The noise shaping function is extracted and implemented specifically in the digital slope ADC circuitry, which operates at lower power. By placing the noise shaping function in the lower-power second circuitry rather than the higher-power first circuitry, the overall system achieves better noise performance without proportionally increasing power consumption.
2Speed
If conventional ADC circuitry is used to achieve high performance, then bandwidth is improved, but power consumption increases
Solution Approach 1:
The conversion process is segmented into two stages with different bandwidth requirements. The first ADC circuitry handles the initial high-bandwidth conversion, while the digital slope ADC circuitry handles subsequent lower-bandwidth conversion steps, allowing the system to maintain high overall bandwidth while reducing the power consumption associated with continuous high-bandwidth operation.
3Measurement precision
If noise reduction is implemented in the ADC, then signal-to-noise ratio is improved, but device complexity increases
Solution Approach 1:
The noise shaping function is extracted and implemented in a dedicated noise shaping circuit within the digital slope ADC circuitry. This separate implementation allows for targeted noise reduction without requiring complete redesign of the entire ADC system, thereby improving signal-to-noise ratio while limiting the increase in overall device complexity.
Solution Approach 2:
The noise shaping circuit uses feedback mechanisms to reshape the noise spectrum, pushing quantization noise to higher frequency bands where it can be filtered out. This feedback-based noise shaping improves the in-band signal-to-noise ratio without requiring proportional increases in circuit complexity.
Data Source
AI summary
An analog-to-digital converter (ADC) device includes an ADC circuitry and a digital slope ADC circuitry. The ADC circuitry is configured to generate first bits and a first voltage according to an input signal. The digital slope ADC circuitry is configured to generate a second voltage at a node according to the first voltage and to gradually adjust the second voltage to generate second bits. After the second bits are generated, the digital slope ADC circuitry is further configured to perform a noise shaping function according to a first residual signal of the node.