Multi-Phase Clock Skew Control With Wide Delay Range
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Solution Overview
Problem
Existing clock control techniques in high-speed serializer/deserializer integrated circuits face challenges with phase mismatches leading to excessive jitter and unreliable data slicing, as they consume high power and offer limited phase delay range.
Innovation Solution
A multi-phase clock control circuit that independently controls clock phases using phase interpolation and variable current sources, allowing for low power consumption and a wide range of phase delays through bi-directional phase adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing clock control techniques are used to control clock phases, then phase matching can be achieved, but power consumption is high and phase delay range is limited
Solution Approach 1:
The patent implements dynamic phase control by making the clock signal paths adjustable through variable delay elements. The system dynamically selects different delay paths based on required phase adjustments, enabling both low power operation (by selecting optimal paths) and wide phase delay range (by having multiple adjustable paths). This resolves the contradiction by making the system adaptable rather than static.
Solution Approach 2:
The patent changes the delay parameter of clock signals through multiple controllable delay elements inserted in the clock paths. By adjusting the delay parameter dynamically, the system achieves wide phase control range while consuming low power (only activating necessary delay elements). This directly addresses both the power consumption and phase delay range requirements.
2Adaptability or versatility
If existing clock control techniques are used to control clock phases, then phase adjustment can be achieved, but the phase delay range is limited
Solution Approach 1:
The patent implements dynamic phase control by making the clock signal paths adjustable through variable delay elements. The system dynamically selects different delay paths based on required phase adjustments, enabling both low power operation (by selecting optimal paths) and wide phase delay range (by having multiple adjustable paths). This resolves the contradiction by making the system adaptable rather than static.
Solution Approach 2:
The patent employs feedback mechanisms to monitor clock phase alignment and automatically adjust delay elements to achieve optimal phase matching. This feedback control ensures reliable data slicing by continuously maintaining proper phase relationships between clock signals, while the intelligent adjustment process achieves wide phase delay range efficiently.
3Measurement precision
If phase interpolation is used to control clock phases, then precise phase control can be achieved, but circuit complexity increases
Solution Approach 1:
The patent segments the clock control function into multiple independent delay elements rather than using a single complex phase interpolator. Each delay element handles a specific portion of the phase adjustment, making the overall system more manageable and less complex while achieving precise phase control through the combination of segmented elements.
Solution Approach 2:
The patent achieves precise phase control by making discrete parameter changes through multiple controllable delay elements rather than using continuous phase interpolation. This approach provides sufficient precision for the application while avoiding the complexity of analog phase interpolation circuits, as each delay element can be independently controlled and optimized.
Data Source
AI summary
A circuit includes, in part, a first transistor receiving a first clock signal at its gate, a second transistor receiving a second clock signal at its gate, a first impedance coupled to the drain terminal of the first transistor, a second impedance coupled to the drain terminal of the second transistor, a current source coupled to the source terminals of the first and second transistors, a third transistor receiving a third clock signal at its gate, a fourth transistor receiving a fourth clock signal at its gate, a fifth transistor coupling the drain terminal of the third transistor to the second impedance in response to a first control signal, a sixth transistor coupling the drain terminal of the fourth transistor to the second impedance in response to a second control signal, and a first variable current source coupled to the source terminals of the third and fourth transistors.