SAR ADC Common-Mode Voltage Correction for Faster Comparison
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Solution Overview
Problem
The use of asynchronous SAR-ADCs in semiconductor devices can lead to insufficient speed due to the influence of common-mode differential input voltage, resulting in prolonged comparison times for comparators.
Innovation Solution
A semiconductor device is designed with a voltage quantizer circuit, a correction code decision circuit, and a common-mode voltage regulator circuit. The voltage quantizer circuit converts differential input voltages into digital signals, while the correction code decision circuit decides a correction code to regulate the common-mode voltage, which is then adjusted by the common-mode voltage regulator circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asynchronous SAR-ADC is used to avoid repetitive operations, then conversion speed should be improved, but comparison time increases due to common-mode differential input voltage influence
Solution Approach 1:
The patent changes the common-mode voltage parameter of the differential input signal to resolve the contradiction. By detecting the common-mode voltage level and adjusting it to an optimal range, the comparison time of the asynchronous SAR-ADC is reduced while maintaining high conversion speed. This involves modifying the voltage parameter dynamically based on detection results.
Solution Approach 2:
The patent implements a feedback mechanism where the common-mode voltage is detected, and based on the detection result, the common-mode voltage level is adjusted back to the optimal range. This closed-loop feedback ensures that the ADC operates at peak performance by continuously correcting the common-mode voltage to prevent excessive comparison times.
2Device complexity
If common-mode voltage is not regulated, then device complexity is reduced, but comparison operation speed decreases
Solution Approach 1:
The patent applies preliminary action by detecting the common-mode voltage level before the comparison operation and adjusting it to the optimal range in advance. This pre-adjustment ensures that when the asynchronous SAR-ADC performs comparison operations, the common-mode voltage is already at the optimal level, maximizing comparison speed without adding complex real-time control circuits.
3Speed
If correction code decision circuit is added to regulate common-mode voltage, then comparison speed is improved, but device complexity increases
Solution Approach 1:
The patent uses parameter changes by implementing a correction code decision circuit that adjusts the common-mode voltage parameter based on detection results. The circuit changes the voltage level to an optimal range, improving comparison speed while keeping the complexity increase minimal through efficient circuit design.
Solution Approach 2:
The correction code decision circuit acts as an intermediary between the voltage quantizer circuit and the common-mode voltage regulator circuit. It processes the detection result and generates appropriate correction codes that regulate the common-mode voltage, thereby improving comparison speed without requiring direct complex interaction between the other circuits.
Data Source
AI summary
High speed of an analog-digital converter of a semiconductor device is achieved. A voltage quantizer circuit includes: a first comparator including a first input transistor inputting differential input voltages, and defining a value of a first bit of a digital signal; and a second comparator including a second input transistor being different from the first input transistor, and defining a value of a second bit of the digital signal. A correction code decision circuit decides a correction code for correcting a common-mode voltage of the differential input voltages, based on a conversion end signal output from the voltage quantizer circuit. A common-mode voltage regulator circuit regulates the common-mode voltage by adding or subtracting a corrected voltage based on the correction code to or from the differential input voltages.