RF DAC Background Timing Skew Measurement Using Transparent Dither
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Solution Overview
Problem
High-speed digital to analog converters (DACs) face significant challenges due to timing skew errors and duty cycle errors caused by process, voltage, and temperature variations, which degrade the quality of the analog output and reduce the Signal-to-Noise-and-Distortion Ratio (SNDR) and spurious free dynamic range (SFDR) performance.
Innovation Solution
A background measurement technique is employed that injects a transparent dither signal into the DAC system, uses an observer analog to digital converter to digitize the output, and performs cross-correlation to extract timing skew errors, allowing for the adjustment of DAC cells to reduce mismatches and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed operation is implemented in DAC, then conversion speed is improved, but timing skew errors increase due to process, voltage, and temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where the output of the DAC is fed back through an observer ADC to measure timing skew errors. The measured errors are then used to adjust the DAC cell timing, creating a closed-loop system that continuously compensates for timing variations caused by high-speed operation, process variations, voltage changes, and temperature fluctuations.
Solution Approach 2:
The DAC system performs self-diagnosis and self-correction by using its own output to measure its own timing skew errors through the observer ADC. The system automatically adjusts its own DAC cell timing based on the measured errors, eliminating the need for external calibration equipment or manual intervention.
2Manufacturing precision
If complex calibration techniques are used to reduce timing skew errors, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent introduces an observer ADC as an intermediary device that bridges the DAC output and the timing skew measurement. This intermediary converts the analog DAC output back to digital form, enabling digital processing and cross-correlation analysis to extract timing skew errors without requiring complex analog measurement circuits or external calibration equipment.
Solution Approach 2:
The patent replaces complex analog timing measurement circuits with digital signal processing techniques. By using digital cross-correlation between the input signal and the observer ADC output, the system achieves precise timing skew measurement without requiring complex analog phase detectors, time-to-digital converters, or other sophisticated analog measurement hardware.
3Measurement precision
If transparent dither signal is injected to enable error measurement, then measurement precision is improved, but signal purity decreases
Solution Approach 1:
The patent applies a transparent dither signal to the DAC input before the actual timing skew measurement is performed. This preliminary action randomizes quantization errors and enhances the visibility of timing skew effects in the output, allowing for more accurate measurement through cross-correlation while the dither's transparency ensures it does not introduce significant distortion.
Data Source
AI summary
Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.