W-2W DAC Temperature Compensation for Body-Effect Linearity
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Solution Overview
Problem
Conventional W-2W current-steering digital-to-analog converters (IDACs) used in phase-change memory devices often suffer from systematic errors, resulting in output current pulses that fail to maintain the correct shape and linearity during SET pulses, affecting the temperature gradient applied to memory storage elements.
Innovation Solution
A circuit design incorporating diode-connected MOS transistors and mirroring MOS transistors with temperature-dependent compensation signals, generated by a proportional-to-absolute-temperature current generator and voltage divider circuit, to mitigate the body effect and ensure linear output current pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional W-2W current-steering digital-to-analog converters are used, then the circuit occupies a small silicon area, but the output current pulses fail to maintain the correct shape and linearity due to systematic errors affecting some transistors
Solution Approach 1:
The IDAC circuit is divided into multiple independent current mirrors, each responsible for generating a specific portion of the output current. This segmentation allows each current mirror to be optimized independently, reducing systematic errors while maintaining the compact W-2W architecture.
Solution Approach 2:
The invention modifies the transistor sizing parameters within the current mirrors to compensate for systematic errors. By carefully adjusting the width-to-length ratios of transistors in each current mirror, the circuit achieves improved linearity and pulse shape while maintaining small silicon area.
2Speed
If the programming current is increased to improve switching speed, then the SET and RESET operations become faster, but the body effect in MOS transistors increases, causing non-linearity in the output current
Solution Approach 1:
The circuit incorporates feedback mechanisms where the output current of each current mirror is monitored and used to adjust the gate voltages of subsequent stages. This feedback compensates for body effect non-linearity, allowing high-speed operation while maintaining precise current linearity.
Solution Approach 2:
The invention uses a composite approach combining multiple current mirrors with different transistor characteristics. By cascading current mirrors with complementary body effect characteristics, the circuit achieves both high-speed operation and linear current output through the composite behavior of the combined structure.
3Manufacturing precision
If temperature compensation is added to mitigate the body effect, then the output current linearity improves, but the device complexity increases
Solution Approach 1:
The current mirrors are designed to self-compensate for temperature-dependent body effects through their inherent circuit topology. The automatic adjustment of gate voltages based on temperature-induced changes eliminates the need for external compensation circuits, maintaining linearity without increasing complexity.
Solution Approach 2:
The same current mirror structure serves multiple functions: it generates the required output current, compensates for body effects, and provides temperature stabilization. This multi-functionality achieves improved linearity without adding separate compensation circuits, thereby avoiding increased device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively compensates for the body effect in W-2W IDACs, producing output current pulses with the desired shape and linearity, thereby improving the precision and reliability of phase-change memory operations.
Implementation Method 1
A diode-connected MOS transistor has a drain terminal connected to an input node and source terminal connected to a reference voltage node. The diode-connected MOS transistor is configured to pass a reference current from the input node to the reference voltage node.
Implementation Method 2
A plurality of ordered mirroring MOS transistors have respective gate terminals connected to a gate terminal of the diode-connected MOS transistor and respective drain terminals alternatively couplable either to a first current node or to a second current node as a function of a plurality of respective ordered control signals.
Implementation Method 3
The mirroring MOS transistors whose source terminal is not directly connected to the reference voltage node have respective bulk terminals configured to receive one or more compensation signals having respective values that decrease with increasing temperature.
Implementation Method 4
generated by a proportional-to-absolute-temperature current generator and voltage divider circuit, to mitigate the body effect and ensure linear output current pulses.
Data Source
AI summary
In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.