Current-Steering DAC Cell Dead-Band Switching for Harmonic Reduction
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Solution Overview
Problem
Current Digital-to-Analog Converters (DACs) suffer from inter-cell interference, leading to odd-order harmonics in the output signal, which limits the peak Signal-to-Noise Ratio (SDNR) and introduces distortion.
Innovation Solution
Incorporating a dead band switch coupled to at least one transistor within a DAC cell, controlled by a periodic signal, to isolate the bias node during data transitions, thereby reducing inter-cell interference and odd-order harmonics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DAC cells are coupled together in a larger circuit, then the DAC can process higher frequency signals with better performance, but inter-cell interference occurs causing odd-order harmonics and distortion
Solution Approach 1:
A dead band switch is introduced as an intermediary component between the bias node and the DAC cell transistor. This switch acts as a mediator that selectively connects or disconnects the bias node during data transitions, thereby reducing inter-cell interference and odd-order harmonics while maintaining signal quality
2Reliability
If a dead band switch is added to reduce inter-cell interference, then odd-order harmonics are reduced and SDNR improves, but device complexity increases
Solution Approach 1:
The bias node connection is segmented into two distinct operational states: connected state during stable periods and disconnected state during data transitions. The dead band switch enables this segmentation by selectively connecting or disconnecting the bias node based on the timing of data transitions, thereby reducing harmonics without requiring complete circuit redesign
Data Source
AI summary
A DAC cell circuit includes: at least a DAC cell, including: a first MOSFET having a drain coupled to a first switch for receiving a first current and coupled to a second switch for generating a second current, a source coupled to ground, and a gate coupled to a first bias voltage; a capacitor coupled between the gate and the drain of the first MOSFET; and a dead-band switch coupled between the gate of the first MOSFET and the bias node. The dead-band switch is controlled by a signal which is periodic with respect to a frequency equal to an input data rate of the DAC cell, and the dead-band switch is open during a data transition.