Single-Die Multi-ADC Timing to Flag Overlap Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing microcontrollers with multiple analog-to-digital converters (ADCs) on a single chip face performance degradation when operating simultaneously due to noise interference, leading to reduced precision and increased manufacturing costs when ADCs are placed on separate semiconductor dies.
Innovation Solution
An integrated circuit (IC) with a first and second ADC disposed on a single semiconductor die, along with logic circuitry that marks digital values obtained during overlapping sampling periods as noisy, allowing for independent operation of multiple ADCs without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple ADCs are placed on separate semiconductor dies, then noise interference between ADCs is eliminated and measurement precision is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent segments the ADC operation into distinct phases (sampling phase and conversion phase) and assigns different priority levels to them. By dividing the operation timeline into phases with different noise sensitivity characteristics, the system can manage multiple ADCs on a single die without severe noise interference, thus avoiding the need for separate semiconductor dies while maintaining measurement precision.
Solution Approach 2:
The patent implements preliminary action by completing the sampling phase before the conversion phase begins. The sampling is performed during a time window where noise from other ADCs is minimized, and the conversion is completed before other ADCs start their sampling. This preliminary timing arrangement prevents noise contamination of the conversion result, achieving high precision without requiring separate dies.
2Ease of manufacture
If multiple ADCs operate simultaneously on a single chip, then manufacturing cost and device size are reduced, but noise interference degrades measurement precision
Solution Approach 1:
The patent applies dynamics by making the ADC operation modes time-varying and adaptive. Different ADCs operate in different phases (sampling or conversion) at different times, creating a dynamic time-division multiplexing scheme. This dynamic operation allows multiple ADCs to share the same chip while each maintains its measurement precision, as the noisy conversion phase of one ADC does not overlap with the sensitive sampling phase of another.
Solution Approach 2:
The patent implements periodic action through cyclic operation of multiple ADCs, where each ADC alternates between sampling phase and conversion phase in a periodic manner. This periodic time-division scheme ensures that when one ADC is in its noisy conversion phase, other ADCs are in their sampling phase, and vice versa, thereby enabling single-chip integration without precision degradation.
3Productivity
If ADC sampling and conversion periods overlap, then productivity is improved by allowing concurrent operations, but noise is introduced during sensitive sampling periods
Solution Approach 1:
The patent uses dynamic phase assignment where ADCs switch between sampling and conversion modes in a time-varying manner. This dynamic control allows the system to maximize productivity by keeping all ADCs active while dynamically managing their phases to prevent noise contamination, achieving concurrent operation without harmful noise interference.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that while one ADC is in conversion phase, another ADC is in sampling phase, and vice versa. This continuous alternating pattern ensures that all ADCs are always performing useful work (either sampling or converting) without idle time, maximizing productivity while the phased operation prevents noise interference during sensitive sampling periods.
Data Source
AI summary
Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.